Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
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20.5.5.2. Transmit Watermark Level

Consider the example where the assumption is made: †

DMA burst length = FIFO_DEPTH - IC_DMA_TDLR

Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit FIFO. Consider the following two different watermark level settings: †

  • Case 1: IC_DMA_TDLR = 16: †
    • Transmit FIFO watermark level = IC_DMA_TDLR = 16: †
    • DMA burst length = FIFO_DEPTH - IC_DMA_TDLR = 48: †
    • I2C transmit FIFO_DEPTH = 64: †
    • Block transaction size = 240: †
Figure 122. Transmit FIFO Watermark Level = 16

The number of burst transactions needed equals the block size divided by the number of data items per burst:

Block transaction size/DMA burst length = 240/48 = 5

The number of burst transactions in the DMA block transfer is 5. But the watermark level, IC_DMA_TDLR, is quite low. Therefore, the probability of transmit underflow is high where the I2C serial transmit line needs to transmit data, but there is no data left in the transmit FIFO. This occurs because the DMA has not had time to service the DMA request before the FIFO becomes empty.

  • Case 2: IC_DMA_TDLR = 48 †
    • Transmit FIFO watermark level = IC_DMA_TDLR = 48 †
    • DMA burst length = FIFO_DEPTH - IC_DMA_TDLR = 16 †
    • I2C transmit FIFO_DEPTH = 64 †
    • Block transaction size = 240 †
Figure 123. Transmit FIFO Watermark Level = 48

Number of burst transactions in block: †

Block transaction size/DMA burst length = 240/16 = 15 †

In this block transfer, there are 15 destination burst transactions in a DMA block transfer. But the watermark level, IC_ DMA_TDLR, is high. Therefore, the probability of I2C transmit underflow is low because the DMA controller has plenty of time to service the destination burst transaction request before the I2C transmit FIFO becomes empty. †

Thus, the second case has a lower probability of underflow at the expense of more burst transactions per block. This provides a potentially greater amount of bursts per block and worse bus utilization than the former case. †

Therefore, the goal in choosing a watermark level is to minimize the number of transactions per block, while at the same time keeping the probability of an underflow condition to an acceptable level. In practice, this is a function of the ratio of the rate at which the I2C transmits data to the rate at which the DMA can respond to destination burst requests. †