Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.4.6.1. Taking the NAND Flash Controller Out of Reset

When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset until software releases it.

After the Cortex-A53 MPCore boots, it can deassert the reset signal by clearing the appropriate bits in the reset manager's corresponding reset register. For details about reset registers, refer to section: Reset Signals and Registers in the Reset Manager chapter.

You should ensure that both the NAND ECC RAM and the NAND Module resets are deasserted before beginning transactions. Program the nandocp bits and the nand bits in the per0modrst register of the Reset Manager to deassert reset in the NAND ECC RAM and the NAND module, respectively.