Quartus Prime Help version 15.1

Content
Search
Loading, please wait ...

Loading

  • Welcome to the Software
    • Welcome to the Quartus Prime Software
      • New Features in this Release
      • Using Help Effectively
  • Managing Projects
    • Viewing Project Information
      • General Page (Options Dialog Box)
      • Project Navigator Window
      • Libraries Page
      • About the Project Navigator
        • Hierarchy Tab:
        • Files Tab:
        • Design Units Tab:
        • Revisions Tab:
        • IP Components Tab:
    • General Settings
      • Libraries Page
      • Options Dialog Box
      • Colors Page (Options Dialog Box) (All Editors)
      • Fonts Page (Options Dialog Box) (All Editors)
      • General Page (Options Dialog Box)
      • License Setup Page (Options Dialog Box)
      • Processing Page (Options Dialog Box)
    • Project Settings
      • Settings Dialog Box
      • General Page (Settings Dialog Box)
      • Libraries Page (Settings Dialog Box)
      • Files Page (Settings Dialog Box)
      • Incremental Compilation Page (Settings Dialog Box)
      • VHDL Input Page (Settings Dialog Box)
      • Verilog HDL Input Page (Settings Dialog Box)
      • Default Parameters Page (Settings Dialog Box)
      • Start Design Assistant Command (Processing Menu)
      • SignalTap II Logic Analyzer Page (Settings Dialog Box)
      • Logic Analyzer Interface Page (Settings Dialog Box)
      • PowerPlay Power Analyzer Settings Page (Settings Dialog Box)
      • SSN Analyzer Page (Settings Dialog Box)
    • Power Settings
      • Operating Settings and Conditions Page (Settings Dialog Box)
      • Voltage Page (Settings Dialog Box)
      • Temperature Page (Settings Dialog Box)
    • Software Connectivity
      • Quartus Prime TalkBack Dialog Box
      • Internet Connectivity Page (Options Dialog Box)
    • Customize Flow Dialog Box
  • About Simulating Designs
  • Running Timing Analysis
    • New SDC File Command (TimeQuest Timing Analyzer)
    • Open SDC File Command (TimeQuest Timing Analyzer)
    • Read SDC File Command
    • Report Recovery Summary Command
    • Report Removal Summary Command
    • Report False Path Dialog Box
  • Timing Analysis Settings
    • Set Clock Groups Dialog Box (set_clock_groups)
    • Set Clock Latency Dialog Box (set_clock_latency)
    • Set Clock Uncertainty Dialog Box (set_clock_uncertainty)
    • Set False Path Dialog Box (set_false_path)
    • Set Input Delay Dialog Box (set_input_delay)
    • Set Maximum Delay Dialog Box (set_max_delay)
    • Set Minimum Delay Dialog Box (set_min_delay)
    • Set Multicycle Path Dialog Box (set_multicycle_path)
  • Integrating Other EDA Tools
    • About Using EDA Simulators
    • Integrating EDA Tools with NativeLink
  • Simulation Settings
    • About Integrating Other EDA Tools
    • Preparing for EDA Simulation
    • Running EDA Simulators
  • Simulation Tools
    • Active-HDL
      • Performing a Simulation of a Verilog HDL Design with the Active-HDL Software
      • Performing a Simulation of a VHDL Design with the Active-HDL Software
    • ModelSim
      • Setting Up a Project with the ModelSim Software
      • Performing a Timing Simulation with the ModelSim Software
    • ModelSim-Altera
      • Setting Up a Project with the ModelSim-Altera Software
      • Performing a Functional Simulation with the ModelSim-Altera Software
      • Performing a Timing Simulation with the ModelSim-Altera Software
    • Incisive Enterprise Simulator
      • Performing a Functional Simulation with the Incisive Enterprise Simulator Software
      • Performing a Timing Simulation with the Incisive Enterprise Simulator Software
    • QuestaSim
      • Setting Up a Project with the QuestaSim Software
      • Compiling Libraries and Design Files with the QuestaSim Software
      • Performing a Functional Simulation with the QuestaSim Software
      • Performing a Timing Simulation with the QuestaSim Software
    • Riviera-PRO
      • Performing a Functional Simulation with the Riviera-PRO Software
      • Performing a Post-Synthesis Simulation with the Riviera-PRO Software
      • Performing a Gate-Level Simulation with the Riviera-PRO Software
    • VCS MX
      • Performing a Functional Simulation with the VCS MX Software
      • Performing a Timing Simulation with the VCS MX (VHDL) Software
    • VCS
      • Performing a Functional Simulation with the VCS Software
      • Performing a Timing Simulation with the VCS Software
  • Design Entry/Synthesis Tools
    • Precision RTL Synthesis Software
      • About Using the Precision RTL Synthesis Software with the Quartus Prime Software
      • Setting Up the Precision RTL Synthesis Working Environment
      • Creating a Design for Use with the Precision RTL Synthesis Software
      • Setting Up a Project with the Precision RTL Synthesis Software
      • Assigning Design Constraints with the Precision RTL Synthesis Software
      • Generating EDIF Netlist Files with the Precision RTL Synthesis Software
    • Synplify Software
      • Setting Up the Synplify Working Environment
      • Creating a Design for Use with the Synplify Software
    • Setting Up the DK Design Suite Working Environment
  • EDA Formal Verification Tools
    • Encounter Conformal Software
      • Setting Up the Encounter Conformal Working Environment
      • Performing Formal Verification with the Encounter Conformal Software
  • EDA Physical Synthesis Tools
  • Generating Output Files for Board-Level Tools
    • Generating Board-Level Timing Analysis Files
      • Setting Up the Tau Working Environment
      • Creating Stamp Model Files with the Quartus Prime Software
      • Performing Timing Verification with the Tau Software
    • Generating Board-Level Symbol Output Files
      • Generating FPGA Xchange-Format Files for Use with Other EDA Tools
      • Generating PartMiner edaXML-Format Files for Use with Other EDA Tools
    • Generating Board-Level Signal Integrity Analysis Files
      • Generating IBIS Output Files with the Quartus Prime Software
      • Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis
    • Generating Boundary-Scan Description Language Files
      • Create Board-Level Boundary-Scan File Window (File Menu)
      • Generating Boundary-Scan Description Language Output Files with the Quartus Prime Software
  • Synopsys-Provided Logic Libraries
  • Example of Performing a Timing Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
  • Using Project Revisions
    • Revisions Dialog Box
    • Compare Revisions Dialog Box
    • Create Revision Dialog Box
  • Archiving Projects
    • Advanced Archive Settings Dialog Box
    • Archive Project Dialog Box
  • Managing Project Databases
  • Creating Designs
    • Using the Block Editor
      • Block Diagram/Schematic File (New Dialog Box)
      • Block Properties Dialog Box (Shortcut Menu)
      • Block Symbol File (New Dialog Box)
      • Bus Properties Dialog Box
      • Conduit Properties Dialog Box
      • Create Design File from Selected Block Dialog Box
      • Create HDL Design File for Current File Dialog Box
      • Create AHDL Include Files for Current File Dialog Box (Block Editor)
      • Create Symbol Files for Current File Command (File Menu) (Block Editor)
      • Edit Selected Symbol Command (Shortcut Menu)
    • Using the Memory Editor
      • Go To Dialog Box
      • New Memory Initialization File Command (Quartus Prime Menu)
      • Open Memory Dialog Box
      • Show Delimiter Spaces Command (View Menu)
    • Using the Text Editor
      • Autocomplete Text Command (Edit Menu)
      • Create VHDL Component Declaration Files for Current File Command (File Menu)
      • Create AHDL Include Files for Current File Command (File Menu)
      • Create Symbol Files for Current File Command (File Menu)
      • Create Verilog Instantiation Template Files for Current File Command (File Menu)
      • Insert Constraint Command (Shortcut Menu)
      • Insert File Command (Edit Menu)
      • Insert Template Dialog Box
      • Open AHDL Include File Command (Shortcut Menu)
      • Preferred Text Editor (Options Dialog Box)
      • Text Editor Page (Options Dialog Box)
  • Using HDL with the Quartus Prime Software
    • Quartus Prime Primitives
      • Primitives
      • List of Primitives
        • ALT_BIDIR_BUF Primitive
        • ALT_BIDIR_DIFF Primitive
        • ALT_INBUF Primitive
        • ALT_INBUF_DIFF Primitive
        • ALT_IOBUF Primitive
        • ALT_IOBUF_DIFF Primitive
        • ALT_OUTBUF Primitive
        • ALT_OUTBUF_DIFF Primitive
        • ALT_OUTBUF_TRI Primitive
        • ALT_OUTBUF_TRI_DIFF Primitive
        • AND Primitive
        • BAND (Block Design Files only) Primitive
        • BIDIR or INOUT Primitive/Port
        • BNAND (Block Design Files only) Primitive
        • BNOR (Block Design Files only) Primitive
        • BOR (Block Design Files only) Primitive
        • CARRY_SUM Primitive
        • CASCADE Primitive
        • CONSTANT Primitive
        • DFF Primitive
        • DFFE Primitive
        • DLATCH Primitive
        • EXP Primitive
        • GLOBAL Primitive
        • GND (Block Design Files only) Primitive
        • INPUT or IN Primitive/Port
        • JKFF Primitive
        • JKFFE Primitive
        • LATCH Primitive
        • LCELL Primitive
        • LUT_INPUT Primitive
        • LUT_OUTPUT Primitive
        • NAND Primitive
        • NOR Primitive
        • NOT Primitive
        • OPNDRN Primitive
        • OR Primitive
        • OUTPUT or OUT Primitive/Port
        • PARAM Primitive
        • Primitive/Port Interconnections
        • SOFT Primitive
        • SRFF Primitive
        • SRFFE Primitive
        • TFF Primitive
        • TFFE Primitive
        • Title Block Primitive
        • TRI Primitive
        • Unused Inputs to Primitives, Megafunctions & Macrofunctions
        • VCC (Block Design Files only) Primitive
        • WIRE (Block Design Files only) Primitive
        • XNOR Primitive
        • XOR Primitive
        • Pinstub Names in Primitives
        • WYSIWYG Atom Names Unavailable for Use as Primitive Instance Names
    • Quartus Prime Managing IP
      • About the IP Catalog and Parameter Editor
      • Upgrade IP Components Dialog Box
      • Megafunctions/LPM
  • HDL Language Support
    • Quartus Prime Support for VHDL 2008
    • New Features in VHDL 1993
    • Quartus Prime Support for Verilog 2001
    • Verilog HDL Reserved Words
    • Quartus Prime Verilog HDL Support
  • Working with Qsys
    • Qsys Component Editor
      • Add Commands (Templates Menu) (Component Editor)
      • Qsys Component Editor
      • Template Command (Qsys Component Editor)
      • Files Tab (Qsys Component Editor)
      • Parameters Tab (Qsys Component Editor)
      • Interfaces Tab (Qsys Component Editor)
    • Working with Instance Parameters in Qsys
      • Instance Parameters Tab (View Menu) (Qsys)
    • Working with Presets in Qsys
      • New Preset Dialog Box (Qsys)
      • Presets Tab (Qsys)
      • Update Preset Dialog Box (Qsys)
    • Create a Qsys System
      • Add Commands (Templates Menu) (Component Editor)
      • Custom Layouts (View Menu) (Qsys)
      • Interconnect Requirements Tab (View Menu) (Qsys)
      • Messages Tab (View Menu) (Qsys)
      • New Component Command (File Menu) (Qsys)
      • New System Command (File Menu) (Qsys)
      • Add Instance Dialog Box (Qsys)
      • Create Snythesis File From Signals Dialog Box (Qsys)
      • IP Catalog (View Menu) (Qsys)
    • Qsys Commands
      • Assign Custom Instruction Opcodes Command (System Menu) (Qsys)
      • Assign Base Addresses Command (System Menu) (Qsys)
      • Assign Interrupt Numbers (System Menu) (Qsys)
      • Browse Project Directory (File Menu) (Qsys)
      • Create Global Reset Network Command (System Menu) (Qsys)
      • Generate Example Design (Generate Menu) (Qsys)
      • Lock/Unlock Base Address Commands (Edit Menu) (Qsys)
      • Nios II Software Build Tools for Eclipse Command (Tools Menu) (Qsys)
      • Nios II Command Shell [gcc4] Command (Tools Menu) (Qsys)
      • Parameters Tab (View Menu) (Qsys)
      • Recent Projects (File Menu) (Qsys)
      • Refresh System Command (File Menu) (Qsys)
      • Remove Dangling Connections Command (System Menu) (Qsys)
      • Reset to IP Layout (View Menu) (Qsys)
      • Reset to System Layout (View Menu) (Qsys)
      • Show System With Qsys Interconnect Command (System Menu) (Qsys)
      • Upgrade IP Cores Dialog Box (System Menu) (Qsys)
      • Options Dialog Box (Tools Menu) (Qsys)
    • View a Qsys System
      • Assignments Tab (View Menu) (Qsys)
      • Block Symbol Tab (View Menu) (Qsys)
      • Connections Tab (View Menu) (Qsys)
      • Custom Layouts (View Menu) (Qsys)
      • Element Docs Tab (Qsys)
      • Hierarchy Tab (View Menu) (Qsys)
      • Parameters Tab (View Menu) (Qsys)
      • Reset Domains (View Menu) (Qsys)
      • Schematic Tab (View Menu) (Qsys)
      • Set Color (Edit Menu) (Qsys)
      • Clock Domains (View Menu) Qsys)
      • Create Snythesis File From Signals Dialog Box (Qsys)
      • Address Map Tab (View Menu) (Qsys)
      • System Contents Tab (View Menu) (Qsys)
    • Generate in Qsys
      • Generate Example Design (Generate Menu) (Qsys)
      • Generate Testbench System (Generate Menu) (Qsys)
      • Generate HDL (Generate Menu) (Qsys)
      • Generate Example Design (Generate Menu) (Qsys)
    • Debug in Qsys
      • Instrumentation Tab (View Menu) (Qsys)
  • Constraining Designs
    • Group Dialog Boxes
    • All Pins List Command (View Menu)
    • Assign Up, Down, Right, Left, and One by One Commands (Edit Menu)
    • Resources Window (View Menu)
    • Back-Annotate Assignments Dialog Box
    • Back-Annotate Command (Shortcut Menu) (Pin Planner)
    • Board Trace Model Window (View Menu)
    • Early Pin Planning Dialog Box
    • Create Top-Level Design File Dialog Box
    • Customize Filter Dialog Box
    • Pin Migration View Window (View Menu)
    • Edit Megafunction (Shortcut Menu)
    • Find Swappable Pins Dialog Box
    • Groups List Command (View Menu)
    • Enable Live I/O Check Command (Processing Menu)
    • Live I/O Check Status Window (View Menu)
    • Location Dialog Box
    • New Filter Dialog Box
    • Node Filter Dialog Box
    • Pad View Window (View Menu)
    • Pin Finder Dialog Box
    • Pin Legend Window (View Menu)
    • Pin Planner Page (Options Dialog Box)
    • Pin Planner Command (Assignments Menu)
    • Properties Dialog Boxes
    • Remove Assignments Dialog Box (Assignments Menu)
    • Reserve Commands (Shortcut Menu)
    • Set Up Top-Level Design File Window (Edit Menu)
    • Show Commands (View Menu/Task Window) (Pin Planner)
    • Show Assignable Pins (Shortcut Menu)
    • Show Commands (Shortcut Menu) (Pin Migration View Window)
    • Show SSN Analyzer Results (View Menu) (Pin Planner)
    • Task and Report Windows (Pin Planner)
    • Assignment Categories Dialog Box
    • Advanced Import Settings Dialog Box
    • Import Assignments Dialog Box (Assignments Menu)
    • Start I/O Assignment Analysis Command (Processing Menu)
    • Assignment Editor Command (Assignments Menu)
    • Customize Columns Dialog Box
    • Node Finder Command (View Menu)
    • Customize Filter Dialog Box
    • New Custom Filter Dialog Box
    • Select Hierarchy Level Dialog Box
  • Using Advisors for Design Optimization
    • About Advisors in the Quartus Prime Software
    • Arria 10 to Stratix 10 Migration Advisor Command (Tools Menu)
    • Compilation Time Advisor Command (Tools Menu)
    • Pin Advisor Command (Tools Menu)
    • Power Optimization Advisor Command (Tools Menu)
    • Tips and Tricks Command (Help Menu)
    • Resource Optimization Advisor Command (Tools Menu)
    • Timing Optimization Advisor Command (Tools Menu)
  • Viewing Reports and Messages
    • List of Compilation and Simulation Reports
    • Manipulating Compilation or Simulation Report Window Output
    • Message Suppression Manager Dialog Box
    • Messages Page (Options Dialog Box)
  • Compiling Designs
    • Start Compilation Command (Processing Menu)
    • Start Analysis and Synthesis Command (Processing Menu)
    • More Compilation Process Settings Dialog Box
    • Device and Pin Options Dialog Box
    • Integrated Synthesis
    • Place & Route
    • Incremental Compilation
      • Import Design Partition Dialog Box
      • Advanced Import Settings Dialog Box
      • Export Design Partition Dialog Box
      • Export Design Partition Settings Dialog Box
    • Partial Reconfiguration
    • Assembler Programming Files
  • Generating Programming Files
    • Start Assembler Command (Processing Menu)
    • Add JTAG ID Dialog Box
    • Export User-Defined Device Dialog Box
    • Import User Devices Dialog Box
    • Edit Device Dialog Box
    • Add Hex Data Dialog Box
    • Hexadecimal File Options Dialog Box
    • Hardware Setup Dialog Box
    • Open JTAG Chain Log File Dialog Box
    • New CFI Flash Device Dialog Box
    • New Device Dialog Box
    • OpenCore Plus Status Dialog Box
    • PMSF File Properties Dialog Box
    • Select Device Dialog Box
    • Select Flash Device Dialog Box
    • Select New Flash Device Dialog Box
    • SOF Data Properties Dialog Box
    • SOF File Properties Dialog Box
    • Add Hardware Dialog Box
    • Add Server Dialog Box
    • Configure Local JTAG Server Dialog Box
    • Convert Programming Files - Advanced Options Dialog Box
    • Define CFI Flash Device Dialog Box
    • Device's Properties Dialog Box
  • Debugging and Optimization
    • Debugging with the SignalTap II Logic Analyzer
      • View Page (SignalTap II Logic Analyzer) (Options Dialog Box)
      • Waveform Display Pane (SignalTap II Logic Analyzer)
      • SignalTap II Logic Analyzer Page (Settings Dialog Box)
      • Add Entry Dialog Box
      • Add State Machine Nodes Dialog Box
      • Find Bus Value Dialog Box
      • Import Table Dialog Box
      • Insert Value Dialog Box
      • Add Table Dialog Box
      • Mnemonic Table Setup Dialog Box
      • Object Properties Dialog Box
      • Plug-In Options Dialog Box
      • Print Options Dialog Box (SignalTap II Logic Analyzer)
      • Recreate State Machine Mnemonics Dialog Box
      • Example of Using a Bitwise Object in an Advanced Trigger Condition
      • Example of Using a Comparison Object and Pipelining in an Advanced Trigger Condition
      • Examples of Constructing Advanced Trigger Conditions for the SignalTap II Logic Analyzer
      • Example of Using Data Delay in an Advanced Trigger Condition
      • Example of Using an Edge & Level Detector Object and Logical Conditions in an Advanced Trigger Condition
      • Example of Using a Shift Object in an Advanced Trigger Condition
      • Advanced Trigger Tab (SignalTap II Logic Analyzer)
      • Data Tab (SignalTap II Logic Analyzer)
      • Node List Pane (SignalTap II Logic Analyzer)
      • Object Library Pane (SignalTap II Logic Analyzer)
      • Setup Tab (SignalTap II Logic Analyzer)
      • Signal Configuration Pane (View Menu) (SignalTap II Logic Analyzer)
      • SignalTap II Logic Analyzer Page (Options Dialog Box)
      • State-Based Trigger Flow Tab (SignalTap II Logic Analyzer)
    • Debugging with SignalProbe
      • Start SignalProbe Compilation Command (Processing Menu)
      • SignalProbe Pins Dialog Box
      • Add SignalProbe Pin Dialog Box
    • Debugging with the In-System Memory Content Editor
      • In-System Memory Content Editor Window
    • Debugging with the In-System Sources and Probes Editor
      • Select JTAG Debugging Information File Dialog Box
    • Debugging with the Logic Analyzer Interface
      • Logic Analyzer Interface Editor Window
      • Logic Analyzer Interface Page (Settings Dialog Box)
    • Debugging with the Transciever Toolkit
      • Load Design Dialog Box
      • Transceiver Toolkit Window
      • Specify Management Clock Dialog Box
      • Report Panel (Transceiver Toolkit)
      • System Console
      • About System Console Window
      • Auto Sweep Panel (Receiver/Transceiver)
      • EyeQ Panel (Receiver/Transceiver)
      • Control Channel and Control Link Panels
      • Execute Script Dialog Box
  • Optimizing Designs with the Design Space Explorer
    • Advanced Farm Settings Dialog Box
    • Launch Design Space Explorer Command (Tools Menu)
  • Optimizing Routing with the Chip Planner
    • Resource Property Editor Page (Options Dialog Box)
    • Create Atom Dialog Box
    • Layers Settings Dialog Box
    • Locate History Pane (Chip Planner)
    • Properties Tab (Chip Planner)
    • Report Window (Chip Planner)
    • Report Compilation Messages (Chip Planner)
    • Report HSSI Block Connectivity dialog box (Chip Planner)
    • Report Pins Dialog Box (Chip Planner)
    • Report Placed Pins By I/O Standard
    • Properties dialog box (Chip Planner)
    • Report Resources Dialog Box (Chip Planner)
    • Report Spine Clock Utilization dialog box (Chip Planner)
    • Report Used Clock Regions dialog box (Chip Planner)
    • Report Routing Utilization Dialog Box
    • Tasks Window (Chip Planner)
    • Chip Planner Page (Options Dialog Box)
  • Design Partition Planner
    • About the Design Partition Planner
      • Design Partition Planner Interface
      • Integration with Chip Planner:
      • How to use the Design Partition Planner Efficiently:
    • Design Partition Planner Commands
    • Bundle Configuration Dialog Box (Design Partition Planner)
    • Bundle Properties Dialog Box (Design Partition Planner)
    • Design Partition Planner Page (Options Dialog Box)
    • Design Partition Planner Commands
    • Design Partition Planner Page (Options Dialog Box)
  • Power Estimation and Analysis
    • PowerPlay Power Analyzer Tool Window
    • Start PowerPlay Power Analyzer Command (Processing Menu)
    • Add/Edit Power Input File Dialog Box
    • Generate PowerPlay Early Power Estimator File Command (Project Menu)
    • HPS Power Calulator Dialog Box
    • Select Hierarchy Dialog Box
    • PowerPlay Power Analyzer Assignment Names
  • Signal Integrity Analysis
    • Start SSN Analyzer Command (Processing Menu)
    • SSN Analyzer Tool Window
    • SSN Settings Dialog Box
    • Board Trace Model
    • Signal Integrity Metrics
  • Designing with LogicLock Regions
    • LogicLock Region Properties Dialog Box (Shortcut Menu)
    • Set Size and Origin to Previous Fitter Results Command (Shortcut Menu)
    • Set to Estimated Size Command (Shortcut Menu)
    • Add Node Dialog Box
    • Add/Edit Security Assignments for Signal dialog box
    • Edit Node Dialog Box
    • Export Assignments Dialog Box
    • LogicLock Regions Window
    • Priority Dialog Box
    • Region Filter Dialog Box
    • Rename Region Dialog Box
    • Excluded Element Types Dialog Box
    • Understanding Assignment Priority
    • Recommendation Details Dialog Box
  • Engineering Change Management
  • Using the Netlist Viewer
    • Bird's Eye View Command (View Menu)
    • Copy Image Commands (Edit Menu)
    • Copy Table Command (Shortcut Menu)
    • Hide Selection Commands (Shortcut Menu)
    • Filter Commands (Shortcut Menu)
    • Expand to Upper Hierarchy (Shortcut Menu)
    • Generate HDL File Command (Tools Menu)
    • Input Ports List/Ouput Ports List Commands (View Menu)
    • Properties Pane (Netlist Viewers)
    • RTL Viewer Command (Tools Menu)
    • Generate Other Files Dialog Box
    • Technology Map Viewer Command (Tools Menu)
    • Select Bus Index Dialog Box
    • Find Options Dialog Box (Netlist Viewers)
    • Find Pane (Netlist Viewers)
    • Examples of Primitive Symbols
  • Using the State Machine Editor
    • State Machine Viewer Command (Tools Menu)
    • New State Machine File Command (Quartus Prime Menu)
    • Properties Dialog Boxes (State Machine Editor)
    • State Table Command (View Menu)
  • Working with the Design Assistant
    • Design Assistant Rules Dialog Box
    • Categories, Severity Levels, and Rule IDs for Design Assistant Rules
    • High Fan-Out Net Settings Dialog Box
    • Design Assistant Page (Settings Dialog Box)
    • Custom Rule Settings Dialog Box
    • Finite State Machine Deadlock Settings Dialog Box
    • Gated Clock Settings Dialog Box
    • Global Clock Threshold Setting Dialog Box
    • Report Settings Dialog Box
    • Node Types Eligible for Rule Suppression
    • Non-synchronous Design Structure Rules
      • Design Should Not Contain Combinational Loops (Design Assistant Rule)
      • Register Output Should Not Drive Its Own Control Signal Directly or Through Combinational Logic (Design Assistant Rule)
      • Design Should Not Contain Delay Chains (Design Assistant Rule)
      • Design Should Not Contain Ripple Clock Structures (Design Assistant Rule)
      • Pulses Should Not Be Implemented Asynchronously (Design Assistant Rule)
      • Multiple Pulses Should Not be Generated in Design (Design Assistant Rule)
      • Design Should Not Contain SR Latches (Design Assistant Rule)
      • Design Should Not Contain Latches (Design Assistant Rule)
    • Clock Rules
      • Gated Clock Should be Implemented According to Altera Standard Scheme (Design Assistant Rule)
      • Logic Cell Should Not be Used to Generate Inverted Clock (Design Assistant Rule)
      • Gated Clock is Not Feeding at Least a Pre-Defined Number of Clock Ports to Effectively Save Power (Design Assistant Rule)
      • Clock Signal Source Should Drive Only Input Clock Ports (Design Assistant Rule)
      • Clock Signal Should be a Global Signal (Design Assistant Rule)
      • Clock Signal Source Should Not Drive Registers That are Triggered by Different Clock Edges (Design Assistant Rule)
    • Reset Rules
      • Combinational Logic Used as a Reset Signal Should be Synchronized (Design Assistant Rule)
      • External Reset Should be Synchronized Using Two Cascaded Registers (Design Assistant Rule)
      • External Reset Should be Correctly Synchronized (Design Assistant Rule)
      • Reset Signal That is Generated in One Clock Domain and Used in Other, Asynchronous Clock Domains Should be Synchronized (Design Assistant Rule)
      • Reset Signal That is Generated in One Clock Domain and Used in Other, Asynchronous Clock Domains Should be Correctly Synchronized (Design Assistant Rule)
    • Signal Race Rules
      • Output Enable and Input of Same Tri-State Node Should Not be Driven by Same Signal Source (Design Assistant Rule)
      • Synchronous Port and Asynchronous Port of the Same Register Should Not Be Driven by the Same Signal Source (Design Assistant Rule)
      • More Than One Asynchronous Signal Source of the Same Register Should Not be Driven by the Same Source (Design Assistant Rule)
      • Clock Port and Any Other Signal Port of the Same Register Should Not Be Driven by the Same Source (Design Assistant Rule)
    • Timing Closure Rules
      • Nodes With More Than Specified Number of Fan-Outs (Design Assistant Rule)
      • Top Nodes With Highest Number of Fan-Outs (Design Assistant Rule)
      • Asynchronous Clock Domain Rules
        • Data Bits Are Not Synchronized When Transferred Between Asynchronous Clock Domains (Design Assistant Rule)
        • Multiple Data Bits That are Transferred Across Asynchronous Clock Domains are Synchronized But Not All Bits May Be Aligned in the Receiving Clock Domain (Design Assistant Rule)
        • Data Bits Are Not Correctly Synchronized When Transferred Between Asynchronous Clock Domains (Design Assistant Rule)
  • Devices and Adapters
    • Devices and Adapters
  • Logic Options Definition
  • Quartus Prime Scripting Support
    • About Quartus Prime Scripting
  • Shortcuts
    • Keyboard Shortcuts and Toolbar Buttons
  • Glossary
    • Glossary
  • Tcl Packages and Commands
    • API Functions for Tcl
  • Messages
    • List of Messages