WIRE (Block Design Files only) Primitive

Name:

WIRE

Output Description:

OUT = input

Input Description:

IN

The WIRE primitive is used to rename a node or bus line. WIRE primitives do not have any associated logic behavior.

The WIRE primitive is directional; that is, on a bidirectional bus, you can use only one WIRE primitive to rename the input or output portion of the bus.

Note: In Verilog HDL, the buf gate primitive has the same functionality as the WIRE primitive. For information about primitive instantiation, go to Using a Logic Function.

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