Generate Example Design (Generate Menu) (Qsys)

You can generate a Qsys example design by clicking Generate > Generate Example Design.

The example design provides the top-level HDL definition of your Qsys system in either Verilog HDL or VHDL. This tab also displays VHDL component declarations. You can copy this HDL example and paste it into a top-level HDL file that instantiates the Qsys system, if the system is not the top-level module in your Quartus® Prime Standard Edition project.

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