|
Name: |
Function: |
Default Logic Level: |
||
|---|---|---|---|---|
|
CLK |
= |
register clock input |
none |
|
|
CLRN |
= |
clear input |
VCC (inactive) |
|
|
D, J, K, R, S, T |
= |
data input from logic array |
none |
|
|
ENA |
= |
latch enable or clock enable input |
VCC (active) |
|
|
PRN |
= |
preset input |
VCC (inactive) |
|
|
ADATA |
= |
asynchronous data input |
none |
|
|
ASDATA |
= |
Asynchronous/synchronous data input |
none |
|
|
ALOAD |
= |
asynchronous load input |
GND (inactive) |
|
|
SCLR |
= |
synchronous clear input |
GND (inactive) |
|
|
SLOAD |
= |
synchronous load input |
GND (inactive) |
|
|
Q |
= |
output |
n/a |
|