A design should not contain SR latches, which are structures where two two-input NOR gates or two-input NAND gates (which the Quartus® Prime Standard Edition software implements in logic cells) are cross-coupled using combinational loops that drive the output of one gate to an input of the other gate. The following image shows an example of an SR latch:
An SR latch can cause glitches and ambiguous timing in a design, which makes timing analysis of the design more difficult. In addition, an SR latch can cause significant stability and reliability problems in a design because the behavior of the combinational loops in the latch often depends on the relative propagation delays of the combinational loop's logic, causing the combinational loop to behave differently under different operation conditions.
The Design Assistant also generates this rule for SR latches that are part of more sophisticated latches that the Design Assistant cannot identify.