INPUT or IN Primitive/Port

AHDL Syntax:

in1 : INPUT;

Verilog HDL Example Instantiation:

input in1

VHDL Syntax:

in1 : IN

Source:

Device I/O or dedicated input pins, or higher levels in the hierarchy tree

Destination:

All logic functions except BIDIR, VCC, and GND

In a Block Design File (.bdf) Definition, you can use the Pin Properties dialog box to specify pin properties for this primitive, such as the pin name and default value.

Note:
  • Assigning an unconnected INPUT primitive to a pin number reserves the pin for future use.
  • Only the pin assignments of the top-level entity are used during compilation.
  • For information about primitive instantiation, go to Using a Logic Function.
Related reference

BIDIR or INOUT Primitive/Port
VCC (Block Design Files only) Primitive
GND (Block Design Files only) Primitive
Pin Properties Dialog Box

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