A design should not contain ripple clock structures, that is, structures where the outputs of two or more registers in a cascade each directly drives the input clock port of the following register in the cascade. The following image shows an example of a ripple clock structure:
Each stage of a ripple clock structure causes phase delay, which accumulates and results in large skews in the structure's output signal; the large skew can cause problems when you use the ripple clock structure as a clock signal for other circuits. Each stage of a ripple clock structure also causes a new clock domain to be defined; the additional clock domains make timing analysis of the design more complex and time-consuming.
Ripple clock structures are often used to make counters out of the smallest amount of logic possible. However, in all Altera devices supported by the Quartus® Prime Standard Edition software, using a ripple clock structure to reduce the amount of logic used for a counter is unnecessary because the device allows you to construct a counter using one logic element per counter bit.