Clock Signal Source Should Drive Only Input Clock Ports (Design Assistant Rule)

Clock signal sources in a design should drive only input clock ports of registers. When a design contains clock signal sources that connect to ports other than clock ports, the design is considered asynchronous, which can cause problems in the design.

The following image shows an example of a clock signal source that incorrectly drives the input pin of an AND gate:

This rule does not apply in the following situations:

• When the clock signal source drives combinational logic that is used as a clock signal, and the combinational logic is implemented according to the Altera standard scheme.
• When the clock signal source drives only a clock multiplexer that selects one clock source from a number of different clock sources. However, because this type of multiplexer adds complexity to the timing analysis of a design, you should avoid using the multiplexer in the design.