Synopsys software provides the altera logic library that is used for synthesizing and compiling VHDL and VerilogHDL designs. The altera library
includes the following library files:
| Library |
Description |
|---|
| altera.vhd |
A VHDL logic function library that includes the LCELL, SOFT, GLOBAL, CASCADE, and CARRY
primitives for controlling design synthesis and fitting. These primitives can be instantiated directly in your VHDL file. These models allow you to perform functional VHDL
simulation while maintaining an architecture-independent VHDL description. |
| altera.v |
A VerilogHDL logic function library equivalent to the altera.vhd library file. |
Note: You can create your own libraries of custom logic functions for use with Synopsys software. You can use custom logic functions to incorporate a
Text Design File (.tdf) Definition or any other
Quartus® Prime Standard Edition-supported design file into a project. The
Quartus® Prime Standard Edition software uses the
synplcty.lmfLibrary Mapping File (.lmf) Definition to map standard Synopsys logic functions to equivalent
Quartus® Prime Standard Edition logic functions. To use custom logic functions, you can create a
custom LMF that maps your custom logic functions to the equivalent EDIF Input File, Text Design File (
.tdf) or other design file. For more information, refer to Library
Mapping File Format.