A design should not contain latches, which are structures where two sets of two-input combinational logic (which the Quartus® Prime Standard Edition software implements in logic cells) are cross-coupled using combinational loops that drive the output of one set of logic to an input of the other set of logic. The following image shows an example of a latch:
A latch can cause glitches and ambiguous timing in a design, which makes timing analysis of the design more difficult. In addition, a latch can cause significant stability and reliability problems in a design because the behavior of the combinational loops in the latch often depends on the relative propagation delays of the combinational loop's logic, causing the combinational loop to behave differently under different operation conditions.
The Design Assistant generates this rule when it identifies one or more structures as latches but cannot determine the latch types. As a result, this rule is applied when the Design Assistant identifies a 2-input latch structure that does not resemble an SR latch. The latches may also be part of more sophisticated latches that the Design Assistant cannot identify.