In a design, the data bits that are transferred between asynchronous clock domains should be synchronized.
If the data bits belong to single-bit data, the following guidelines can prevent metastability problems during synchronization of the data bits:
- Synchronize each data bit with the appropriate number of cascading registers in the receiving asynchronous clock domain.
- Trigger cascading registers on the same clock edge.
- Altera recommends against using logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
The following image shows an example of data bits that are transferred between asynchronous clock domains that are not synchronized:
If the data bits belong to multiple-bit data, you should use a handshake protocol to guarantee that all bits of the data bus are stable when the receiving clock domain samples the bus.
If you use handshake protocol, only the data bits that act as REQ (Request) and ACK (Acknowledge) signals should be synchronized. The data bits that belong to multiple-bit data do not need to be synchronized. However, you can ignore the violation on the data bits that use a handshake protocol.
The following image shows an example of the transfer of data bits between asynchronous clock domains where only the REQ and ACK signals are synchronized:
