Generate HDL File Command (Tools Menu)

You access this command by clicking Generate HDL File on the Tools menu in the State Machine Editor.

Allows you to generate a design file from the state machine diagram. You must specify the hardware description language, either Verilog HDL VHDL, or SystemVerilog, used to generate source code.

Note: The new State Machine File (.smf) Definitionand generated Verilog Design File (.v) Definition,VHDL Design File (.vhd) Definition, orSystemVerilog Design File (.sv) Definition are automatically added to the current project.

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