Performing a Timing Simulation with the VCS MX (VHDL) Software

To perform a timing simulation of a Quartus^® Prime Standard Edition generated VHDL Output File (.vho) Definition and the corresponding Standard Delay Format Output File (.sdo) Definition with the Synopsys VCS MX software:

Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VCS MX software to use thetiming simulation libraries during simulation:
```
WORK > <work library>
lpm > <work library>  
altera_mf > <work library>    
<device family>  > 
<work library> <work library> >: <physical path to work library> 
```
Create a work library in the project directory by typing the following command at a command prompt:mkdir<work library>
mkdir <work library>

Note: Altera recommends using the Synopsys VCS MX default library names when you create a library. You should name the VCS MX software libraries as follows:

When you run the VCS MX software independently from the Quartus^® Prime Standard Edition software, you should name your library work.
When you run the VCS MX software automatically from the Quartus^® Prime Standard Edition software, your library is automatically named scsim_work under the current project directory, and the work alias is mapped to the scsim_work directory.

Note: For more information about using EDA simulators, refer to Synopsys VCS and VCS MX Support in the Quartus^® Prime Standard Edition Handbook.