Create Top-Level Design File Dialog Box

Allows you to create a VHDL or Verilog HDL design file containing a top-level entity based on the nodes in the Pin Planner. The entity contained in the file you create using this dialog box becomes the top-level design entity for the project. If you want to make changes to the pin connection setup after creating the top-level design file, you can either make the changes in the Pin Planner and then regenerate the file, or directly edit the top-level design file.