Generate HDL (Generate Menu) (Qsys)

You open this dialog box in Qsys by clicking Generate > Generate HDL.

The Quartus® Prime Standard Edition software uses Qsys-generated synthesis HDL files during compilation. You can generate simulation HDL files, which can include simulation-only features targeted towards your simulator. You can generate simulation files as Verilog, VHDL, or as a mixed-language simulation for use in your simulation environment. The Generation dialog box allows you to choose options to generate Qsys design files for synthesis and simulation.

Note: For more information about simulating a Qsys system, refer to "Simulating a Qsys System" in the Creating a System in Qsys chapter in volume 1 of the Quartus® Prime Standard Edition Handbook, and theSimulating Altera Designs chapter in volume 3 of the Quartus® Prime Standard Edition Handbook.
Related information

Creating a System in Qsys
Simulating Altera Designs

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