Allows you to define paths that the TimeQuest analyzer should not analyze, such as test logic or any other path not relevant to the circuit's operation. You can specify the source (-from), common through elements (- thru), and destination (-to) elements of that path.
The following sections provide more information about specifying options for this constraint:
If you specify a clock as the collection for the source (-from) element, you must specify a clock for the collection in the destination (-to) element. Applying exceptions between clocks applies the exception from all registers or ports clocked by the source (-from) clock to all registers or ports clocked by the destination (-to) clock. Applying exceptions between clocks is more efficient than applying them for specific paths.
If you specify pin names or collections of pins, the source (-from) element must be a clock pin, and the destination (-to) value must be any non-clock input pin to a register. Constraints from clock pins, or to and from cells, apply to all registers in the cell or those clocked by the clock pin.
From (-from):
Specifies the source (a collection Definition of clocks, registers, ports, pins, or cells in the design) in a path to which the timing constraint or exception applies. You can use the Name Finder to build a collection.
Through (-thru):
Specifies the common through elements ( collection Definition of pins or nets in the design) in a path to which the timing constraint or exception applies. You can use the Name Finder to build a collection.
To (-to):
Specifies the destination (a collection Definition of clocks, registers, ports, pins, or cells in the design) in a path to which the timing constraint or exception applies. You can use the Name Finder to build a collection.
SDC command:
Displays and allows you to enter SDC commands for the options you specify in this dialog box.