Control Channel and Control Link Panels

You open these control panels in the following ways:

The following alphabetized settings that appear on the Receiver Channels tab, Transmitter Channels tab, and Transceiver Links tabs allow you to directly control the transmitter or receiver channels or transceiver links with generated test patterns over programming hardware while monitoring the actual performance in real time.

Channel/Link Control

Description

Control Panel
AEQ

Adaptive equalization (AEQ) automatically evaluates and selects the best combination of equalizer settings. The setting applies only to Stratix V devices. When turned on, it automatically turns off Equalization Control. The one-time selection determines the best setting and stops searching. You can use AEQ for multiple, independently controlled receiver channels.

Receiver Transceiver Link
Alias

Name you choose for the channel.

Transmitter Receiver Transceiver Link
Bit error rate (BER)

Specifies errors divided by bits tested since the last reset of the checker.

Receiver

Transceiver Link
Channel address

Logical address number of the transceiver channel.

Transmitter Receiver Transceiver Link
Data rate

Data rate of the channel as read from the project file (.sopcinfo) or data rate as measured by the frequency detector.

To use the frequency detector, turn on Enable Frequency Counter in the Data Pattern Checker IP core and/or Data Pattern Generator IP core, regenerate the IP cores, and recompile the design.

The measured data rate depends on the Avalon management clock frequency as read from the project file (.sopcinfo). If the Avalon clock frequency has changed or was not correctly specified in the .sopcinfo file, then click the button next to the measured PLL refclk frequency to specify the management clock frequency.

Click the refresh button next to the measured Data rateif you make changes to your settings and want to sample the data rate again.

Transmitter Receiver Transceiver Link
DC gain.

Circuitry that provides an equal boost to the incoming signal across the frequency spectrum.

Receiver Transceiver Link
DFE 1st tap value, DFE 2nd tap value, DFE 3rd tap value, DFE 4th tap value, DFE 5th tap value

Decision feedback equalization (DFE) for improving signal quality. 0=off, 1=adaptive, 2= one-time adaptive.One-time mode DFE determines the best tap settings and stops searching. There is also a one-time adaptive mode button that automatically turns on one-time mode and immediately populates converged values into the manual settings lists. Adaptive mode DFE automatically tries to find the best tap values.Taps 1 through 3 apply to supported device families (Arria V GZ, Stratix IV GX, and Stratix V) . Taps 4 and 5 apply to supported device families (Arria V GZ, and Stratix V) .

DFE applies to supported device(Arria V GZ, and Stratix series) families.

Receiver Transceiver Link
Enable word aligner

Forces the transceiver channel to align to the word you specify.

Receiver Transceiver Link
Equalization control

Boosts the high-frequency gain of the incoming signal,thereby compensating for the low-pass filter effects of the physical medium.

AEQ one-time adaptation is supported in Auto Sweep. When used with DFE, you need to use DFE triggered mode or DFE continuous.

Receiver Transceiver Link
EyeQ phase step

For supported device(Arria GZ, Stratix IV, Stratix V family devices) families only, sets the phase step for sampling the data from an offset of the CDR (clock data recovery) data path; set to Off to use the regular clock data recovery (CDR) data path.

Receiver Transceiver Link
EyeQ vertical step

Sets the voltage threshold of the sampler to report the height of the eye (supports Stratix V devices only). Negative numbers are allowed for vertical steps to capture asymmetric eye.

Receiver Transceiver Link

Inject Error

Flips one bitto the output of the data pattern generator to introduce an artificial error

Transmitter Transceiver Link
Number of bits tested

Specifies the number of bits tested since the last reset of the checker.

Receiver

Transceiver Link
Number of error bits

Specifies the number of error bits encountered since the lastreset of the checker.

Receiver

Transceiver Link
Number of preamble beats

The number of clock cycles to which the preamble word is sent before the test pattern begins.

Transmitter Transceiver Link
PLL refclk freq

Channel reference clock frequency as read from the project file (.sopcinfo) or measured reference clock frequency as calculated from the measured data rate.

Transmitter

Receiver Transceiver Link
Preamble word

Word to send out if the preamble mode is used.

Transmitter Transceiver Link

Pre-emphasis 1st post-tap, Pre-emphasis pre-tap, and Pre-emphasis 2nd post-tap

The programmable pre-emphasis module in each transmit buffer boosts high frequencies in the transmit data signal, which may be attenuated in the transmission media. Using pre-emphasis can maximize the data eye opening at the far-end receiver.

Transmitter Transceiver Link
Receiver channel

Specifies the name of the selected receiver channel.

Receiver

Transceiver Link
Reset

Resets the current test

Receiver

Transceiver Link
RX CDR PLL status

Shows the receiver in lock-to-reference (LTR) mode. When in auto-mode, if data cannot be locked, this signal alternates in LTD mode if the CDR is locked to data.

Receiver Transceiver Link
RX CDR data status

Shows the receiver in lock-to-data (LTD) mode. When in auto-mode, if data cannot be locked, the signal stays high when locked to data and never toggles.

Receiver Transceiver Link
Serial loopback enabled

Inserts a serial loopback before the buffers, allowing you to form a link on a transmitter and receiver pair on the same physical channel of the device.

Transmitter Receiver Transceiver Link
Start

Starts the pattern generator or checker on the channel to verify incoming data.

Transmitter Receiver Transceiver Link
Stop

Stops generating patterns you have set for a channel.

Transmitter Receiver Transceiver Link
Test pattern

Test pattern sent by the transmitter channel. Options include PRBS7, PRBS15, PRBS23,PRBS31, LowFrequency, and HighFrequency.

The Data Pattern Checker self-aligns both high and low frequency patterns.

Bypass mode is used to send user-design data.

Transmitter Receiver Transceiver Link
Transmitter channel

Specifies the name of the selected transmitter channel.

Transmitter Transceiver Link
TX/CMU PLL status

Provides status of whether the transmitter channel PLL is locked to the reference clock.

Transmitter Transceiver Link

Use preamble upon start

If turned on, sends the preamble word before starting of the test pattern. If turned off, starts sending the test pattern immediately.

Transmitter Transceiver Link
VOD control

Programmable transmitter differential output voltage.

Transmitter Transceiver Link

You can also use the following Tcl commands to enable DFE.

There are three DFE modes:

Scripting Information

Keyword: void alt_xcvr_reconfig_dfe_set_adaptive_mode

Settings: mode=0 | mode=1 | mode=2

Related reference

Specify Management Clock Dialog Box

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