AND Primitive

Names:

AND2, AND3, AND4, AND6, AND8, AND12

Output Description:

OUT = logical AND of inputs

Input Description:

IN1, IN2, ...IN12= 2, 3, 4, 6, 8, or 12 inputs
Note: In Verilog HDL, you must use the built-in and gate primitive to implement the AND logic function. Go to Using a Verilog HDL Gate Primitive for more information.

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.