Quartus® Prime Standard Edition support for Verilog 2001 is described in the following table. Section numbers match those in the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual. Note that the sections numbers do not always match those in the IEEE Std 1394-2001 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual. This table lists all supported constructs, but lists only the major unsupported constructs.
Section |
Verilog HDL Construct |
Quartus® Prime Standard Edition Support |
---|---|---|
2.8 |
Attributes |
Supported. |
3.2 |
Signed data types |
Supported. |
3.10 |
Arrays |
Supported. |
3.11.2 |
localparam |
Supported. |
4.1 |
New operators: **, <<<, and >>> |
Supported. |
4.2.1 |
+: and -: part-selects |
Supported. |
9.7.5 |
Implicit event_expression list |
Supported. |
12.1.3 |
Generated Instantiation |
Supported. |
12.2.2.2 |
Parameter value assignment by name |
Supported. |
12.3.3 |
Net types in Port Declarations |
Supported. |
12.3.4 |
List of Ports Declarations |
Supported. |
13 |
Configuring the contents of a design |
Not supported. |
19.4 |
`ifdef, `else, `elsif, `endif, `ifndef compiler directives |
Supported. |
Verilog 2001 provides additional reserved words, which are listed below. Reserved words cannot be used as identifiers in Verilog HDL designs.
automatic |
generate |
instance |
library |
unsigned |
cell |
genvar |
liblist |
noshowcancelled |
use |
config |
incdir |
library |
signed |
unsigned |
endgenerate |
include |
localparam |
showcancelled |
|
pulsestyle_onevent |
pulsestyle_ondetect |