Generate Other Files Dialog Box

You open this dialog box by clicking Generate Other Files on the Tools menu in the State Machine Editor.

Allows you to generate a design files from the state machine diagram. You can generate AHDL Include File (.inc) Definition,Block Symbol File (.bsf) Definition, Verilog HDL or VHDL Instantiation Template Files, and Component Declaration File (.cmp) Definition.

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.