Node Types Eligible for Rule Suppression

The following table contains the types of nodes that allow Design Assistant rule suppression.

Important: Important: The Design Assistant is not supported by the Arria10 or MAX 10 device families.

Design Assistant Rule	Rule ID	Specified Node Type
Design Assistant Rule	Rule ID	Combinational	Pin	State	Register	Instance	Entity
Design should not contain combinational loops	A101
Register output should not drive its own control signal directly or through combinational logic	A102
Design should not contain delay chains	A103
Design should not contain ripple clock structures	A104
Pulses should not be implemented asynchronously	A105
Multiple pulses should not be generated in design	A106
Design should not contain SR latches	A107
Design should not contain latches	A108
Gated clock should be implemented according to Altera standard scheme	C101
Logic cell should not be used to generate inverted clock	C102
Gated clock is not feeding at least a pre-defined number of clock ports to effectively save power	C103
Clock signal source should drive only input clock ports	C104
Clock signal should be a global signal	C105
Clock signal source should not drive registers that are triggered by different clock edges	C106
Combinational logic used as reset signal should be synchronized	R101
External reset should be synchronized using two cascaded registers	R102
External reset should be correctly synchronized	R103
Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized	R104
Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized	R105
Output enable and input of same tri-state node should not be driven by same signal source	S101
Synchronous port and asynchronous port of same register should not be driven by same signal source	S102
More than one asynchronous signal source of the same register should not be driven by the same source	S103
Clock port and any other signal port of the same register should not be driven by the same source	S104
Nodes with more than specified number of fan-outs: `<n>`	T101
Top nodes with highest fan-out: `<n>`	T102
Data bits are not synchronized when transferred between asynchronous clock domains	D101
Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain	D102
Data bits are not correctly synchronized when transferred between asynchronous clock domains	D103
Suppress all rules	Z100