A design should not contain any delay chains, which are one or more consecutive nodes that act as a buffer for creating intentional delay. The following images show examples of delay chains:
Delay chains often result from asynchronous design practices and can cause problems, including an increase in a design's sensitivity to operating conditions, and a decrease in a design's reliability. In addition, for all Altera devices supported by the Quartus® Prime Standard Edition software, using a delay chain is unnecessary in purely synchronous circuits that use dedicated clocks.
Messages for this rule can occur when a design contains pre-built MegaCore functions Definition with parameter settings that cause an EDA synthesis tool to not remove all unused logic elements from the design during synthesis. When the messages for this rule occur because of MegaCore functions, the design is still synchronous, and the unused logic elements do not cause problems in the design.
Messages are also reported in circumstances where a delay chain exists on the clock or reset path, but not when a delay chain is used on the data path.
This rule checks for delay chains implemented in the logic cell only. Delay chains in I/O portions of the device are not detected by the Design Assistant.