Generating HSPICE Simulation Deck Files for External Signal Integrity Analysis

To generate HSPICE Simulation Deck File (.sp) Definition in the Quartus® Prime Standard Edition software to perform board-level signal integrity analysis in other EDA tools:

Context for the current task

  1. Click Assignments > Settings.
  2. In the Category list, select EDA Tool Settings > Board-Level.
  3. In the Board-Level Signal Integrity Analysis box, select HSPICE from the Format list.
  4. Type or browse to the location you want to use as the output directory for the HSPICE Simulation Deck files. The default location is <project directory>/board/hspice.
  5. To generate the HSPICE Simulation Deck files, compile the design.
    Note:

    The Quartus® Prime Standard Edition software can generate HSPICE Simulation Deck files for supported device families. For all other families, refer to the HSPICE models section of the Signal Integrity section on the Altera website.

    The EDA Netlist Writer places the HSPICE Simulation Deck files in the specified directory. If you have already compiled the design, and want to specify different EDA tools settings and generate output files without recompiling the design, on the Processing menu, click Start > Start EDA Netlist Writer.

  6. Use the HSPICE Simulation Deck files to perform board-level signal integrity verification with the Synopsys HSPICE circuit simulator software.
Related tasks

Setting Up the EDA Tool Environment
Related reference

Settings Dialog Box
Board-Level Page (Settings Dialog Box)
Start EDA Netlist Writer Command (Processing Menu)
Related information

Altera HSPICE models

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