OUTPUT or OUT Primitive/Port

AHDL Syntax:

out1 : OUTPUT;

Verilog HDL Example Instantiation:

output out1

VHDL Syntax:

out1 : OUT

Source:

All logic functions except BIDIR

Destination:

Device I/O pins or higher levels in the hierarchy tree

In a Block Design File (.bdf) Definition, you can use the Pin Properties dialog box to specify pin properties for this primitive, such as the pin name and default value.

Note:
  • Only the pin assignments of the top-level entity are used during compilation.
  • For information about primitive instantiation, go to Using a Logic Function.
Related reference

BIDIR or INOUT Primitive/Port
Pin Properties Dialog Box

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