Board Trace Model

The board trace model describes a board trace and termination network as a set of capacitive, resistive, and inductive parameters. Advanced I/O Timing and the SSN Analyzer use the model to simulate the output signal from the output buffer to the far end of the board trace. Advanced I/O Timing provides accurate timing estimates from the output buffer to the FPGA pin and board trace delay values. Advanced I/O Timing also performs simple signal integrity analyses at the FPGA pin and at the far end of the board trace. The SSN Analyzer analyzes voltage noise on each input, output, and pseudo-differential pin, caused by simultaneous switching of output pins in the design.

You can specify a board trace model for each I/O standard on the Board Trace Model page of the Device and Pin Options dialog box. With supported device(ArriaIIGX, ArriaIIGZ, CycloneIII, StratixIII, StratixIV, and StratixV) families, you can specify a board trace model for individual pins in the Board Trace Model window of the Pin Planner. In the absence of a unit prefix, the Quartus^® Prime Standard Edition software assumes whole units, as indicated in the list of parameters below. If you want to specify a unit prefix symbol, you can type one of the following symbols immediately after the numeric value:

For differential I/O standards, Advanced I/O Timing uses two symmetrical board trace models. You specify board trace assignments to the positive end of the differential pin pair, and the specified assignments are automatically applied to the corresponding value on the negative end. The Quartus^® Prime Standard Edition software ignores board trace model assignments made directly to the negative end of the differential pin pair. To remove a parameter from the model, you can type open or short, as specified in the following list of parameters.