Visible to Intel only — GUID: abn1697544564848
Ixiasoft
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
Visible to Intel only — GUID: abn1697544564848
Ixiasoft
4.7. Connect the Precision Time Protocol Interface
The Pecisio Time Potocol (PTP) iteface is available whe you select the Eable IEEE 1588 PTP optio i the PTP tab. Whe selected, the IP geeates PTP based 1-step o 2-step TX ad RX timestamps. The IP equies the IEEE 1588 96-bit time-of-day (TOD) iput.
The followig diagam shows the sigals associated with the IEEE 1588 PTP suppoted featue.
Figue 47. PTP Iteface Sigals associated with the IEEE 1588 PTP suppoted featue
Pot Name | Width | Domai | Desciptio |
---|---|---|---|
i_clk_tx_tod | 1 | N/A | Clock associated with TX Time-of-Day iput.
Fequecy:
|
i_clk_x_tod | 1 | - | Clock associated with RX Time-of-Day iput.
Fequecy:
|
i_clk_ptp_sample | 1 | - | Sample clock fo PTP measuemet. Sigle sample clock souce ca be shaed by all PTP logics withi a Agilex™ 5 device. Fequecy: 114.2857 MHz (Requied peiod = 8.750 s) |