GTS Ethernet Intel® FPGA Hard IP User Guide

Download PDF
ID 817676
Date 10/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Simulation Output
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence 11.3. Use Signal Tap Analyzer for Troubleshooting
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface A.5. Auto-Negotiation and Link Training
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

6.5.3. Run the Hardware Test

Follow these steps to test the hadwae desig example o the System Cosole:
  1. Ope Tools > System Debuggig Tools > System Cosole o type the commad: 
    system-cosole &
  2. I the TCl Cosole widow, type cd hwtest to chage diectoy to <desig_example_di>/hadwae_test_desig/hwtest.
  3. Type souce mai_10G.tcl to list the available JTAG mastes.
  4. Type set_jtag <idex> to select the appopiate JTAG maste.
  5. Ru oe of the followig commads:
    • If you use the iteal seial loopback, ete the followig commad:
      u_test
    • If you iseted a exteal loopback plug ito the desied Etheet pot, ete the followig commad:
      u_test_without_loopback
  6. The hadwae desig example uses the u_test/u_test_without_loopback commad to iitiate packet tasmissio fom the packet geeato to the IP coe. Specifically, the scipt pefoms the followig tasks:
    • chkphy_status: Displays the clock fequecies ad PMA PHY lock status.
    • chkmac_stats: Displays the MAC statistics coutes.
    • clea_all_stats: Cleas the IP coe statistics coutes.
    • stat_pkt_ge: Stats the packet geeato.
    • stop_pkt_ge: Stops the packet geeato.
    • u_test: Tus o iteal seial loopback.
    • u_test_without_loopback: Tus off iteal seial loopback.
    • eg_ead <add>: Retus the IP coe egiste value at <add>. Example to ead the TX datapath PCS eady egiste: Type eg_ead 0x322.
    • eg_wite <add> <data>: Wites <data> to the IP coe egiste at addess<add>. Example to iitiate soft eset o RX datapath: Type eg_wite 0x108 0x0004.
  7. Veify that the output of the TCL scipt matches the output fom a sample test u, show below. 
    % u_test
--- Tuig off packet geeatio ----
--------------------------------------
--- Eablig Loopback... ---
----------------------------------------
Seial loopback o INST_NUM:0 Lae# 3 is disabled

---Assetig CSR RX Reset ----
Value fom issp eset pobe is 0xcd/0b11001101
1. 0x6A340 	 
2. 0x0006a340	 
Pollig Successfull Bit 15: 0x000001 , Bit 14: 0x000000
1. 0x62340	 
2. 0x00062340	 
Pollig Successfull Bit 15: 0x000000 , Bit 14: 0x000000
---Releasig CSR Reset ---- 
 	 	 
Seial loopback o INST_NUM:0 Lae# 3 is eabled
.............Wait fo RX clock to settle... 

-------- Pitig PHY status ---------
--------------------------------------
 RX PHY Registe Access: Checkig Clock Fequecies(KHz)
	TXCLK 		:161130  (KHZ) 
	RXCLK 		:161130  (KHZ) 

 TX PLL Lock Status           0x00000001 
 RX Fequecy Lock Status     0x00000001 
 RX PCS Ready                 0x1
 TX Laes Stable              0x1
 Deskewed status                0x0
 Lik Fault Status            0x00000000
 RX Fame Eo               0x00000000
 RX AM LOCK Coditio         0x1 

---- Cleaig packet coutes --------------------------
---  IP_INST[0]-----
--------------------------------------------------------
---

--------- Sedig packets... ---------
--------------------------------------
 
----- Readig packet coutes -----
--------------------------------------
 
Tx Stat Packet Coute :16
Tx Ed Packet Coute   :16
Rx Stat Packet Coute :16
Rx Ed Packet Coute   :16
Rx Eo Coute        :0
--------------------------------------

u_test:pass
--------------------------------------

---------------- Doe ----------------
 
 Seial loopback o INST_NUM:0 Lae# 3 is eabled 
 
---Assetig CSR RX Reset ---- 
Value fom issp eset pobe is 0xcd/0b11001101
 1. 0x0A340 
 2. 0x0000a340
Pollig Successfull Bit 15: 0x000001 , Bit 14: 0x000000
 1. 0x02340
 2. 0x00002340
Pollig Successfull Bit 15: 0x000000 , Bit 14: 0x000000
---Releasig CSR Reset ---- 
 
 Seial loopback o INST_NUM:0 Lae# 3 is disabled
Level Two Title