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Ixiasoft
Visible to Intel only — GUID: abn1716940465590
Ixiasoft
4.4.3.2. Connect the RX MAC Flow Control Interface
All interface signals are clocked by the i_clk_tx clock. For 10GE/25GE channels, all interface signals are asynchronous.
Signal Name | Width (bits) | Description |
---|---|---|
o_rx_pause | 1 bit | When asserted, stop sending Ethernet frames on the TX MAC client interface since the IP core received a PAUSE XOFF frame. |
o_rx_pfc[7:0] | 8 bits | When a bit is asserted, stop sending Ethernet frames on the TX MAC client interface for the corresponding priority queue since the IP core received a PFC XOFF frame. |
The o_rx_pause and o_rx_pfc[7:0] ports on each channel are asserted when their remote link partner sets one or more of the queues to a non-zero pause quanta.
- When a PAUSE XOFF request is received and Stop TX traffic when link partner sends pause parameter is enabled in GUI, the TX MAC stops sending traffic.
- When a PAUSE XOFF request is received and Stop TX traffic when link partner sends pause parameter is disabled in the GUI, the TX MAC sends traffic. o_rx_pause deasserts on every valid cycle in the IP. The width of the pulse indicates the number of cycles of pause required.
- For all channels, one quanta is worth multiple cycles of pause. Each quanta is worth 512 cycles.
- o_rx_pfc is asserted when the remote link partner sends a PFC XOFF request. In the diagram below, a PFC (Priority Flow Control) request is sent for queue[0], and then later for queue[6].