GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 10/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Simulation Output
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence 11.3. Use Signal Tap Analyzer for Troubleshooting
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface A.5. Auto-Negotiation and Link Training
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

8.3.1. Simulation Testbench Flow

The testbech executes the followig activity fo MAC with PTP eabled mode:

  1. Asset global eset (i_st_) to eset the GTS Etheet Itel® FPGA Had IP.
  2. Wait util eset ackowledgmet. The o_st_ack_ sigal goes low.
  3. Deasset the global eset.
  4. Wait util o_tx_laes_stable bit is set to 1, idicatig TX path is eady.
  5. Wait util o_x_pcs_eady bit is set to 1, idicatig RX path is eady.
  6. Pefom the PTP use flow util tx_ptp_eady ad x_ptp_eady sigals ae set to 1.
  7. Wite to PTP Asymmety Delay ad pee-to-pee MeaPathDelay Avalo® memoy-mapped iteface egistes.
  8. Reset the PTP moito.
  9. Istuct packet cliet to tasmit data. Wite 0x1 to bit 0 of hadwae packet cliet cotol hw_pc_ctl egiste 0x00 to stat packet geeato.
  10. Read RX packet data ifomatio fom 0x38 - 0x4C egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the RX packet statistics.
    • 0x38/0x3C: RX stat of packet coute (LSB/MSB)
    • 0x40/0x44: RX ed of packet coute (LSB/MSB)
    • 0x48/0x4C: RX eo coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  11. Read TX packet data ifomatio fom 0x00 - 0x34 egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the TX packet statistics.
    • 0x20/0x24: TX stat of packet coute (LSB/MSB)
    • 0x28/0x2C: TX ed of packet coute (LSB/MSB)
    • 0x30/0x34: TX eo coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  12. Compae ead coutes to esue 16 packets wee set ad eceived.
  13. Istuct packet cliet to stop data tasmissio ad clea the coutes by witig hw_pc_ctl[2:0]=3'b100 to stop the packet geeato.
  14. Stat the PTP checke.
    1. Wait util the packet tasmissio is complete. Poll the TX_PKT_VALID bit to moito the tasmissio status.
    2. Read TX packet data ifomatio fom 0x102 - 0x104 egistes i sequetial ode, statig fom the 0x102 egiste. The PTP moito logic efeshes the 0x102 - 0x104 egistes cotet to ext data whe ead fom 0x104 egiste.
    3. Repeat the pevious step util the TX_PKT_EOP bit is set to 1 idicatig the ead opeatio eached the ed of the packet.
    4. Read TX PTP commad ifomatio fom 0x105 - 0x10A egistes i sequetial ode, statig fom the 0x105 egiste. The PTP moito logic efeshes the 0x105 - 0x10A egistes cotet to ext data whe ead fom 0x10A egiste.
    5. If TX PTP commad idicates a PTP packet:
      1. Wait util the TX egess timestamp is available. Use the TX_PTP_ETS_VALID sigal to moito the status.
      2. Read the TX egess timestamp fom the 0x10C - 0x10F egistes i sequetial ode, statig with the 0x10C egiste.
      The PTP moito logic efeshes cotet of 0x10C - 0x10F egistes to ext data whe ead fom the 0x10F egiste.
    6. Wait util the packets ae looped backe i the RX data path. Poll the RX_PKT_VALID bit to moito the tasmissio status.
    7. Read RX packet data ifomatio fom 0x110 - 0x112 egistes i sequetial ode, statig with the 0x110 egiste. The PTP moito logic efeshes the 0x110 - 0x112 egistes cotet to ext data whe ead fom 0x112 egiste.
    8. Repeat the pevious step util the RX_PKT_EOP bit is set to 1 idicatig the ead opeatio eached the ed of the packet.
    9. Read RX igess timestamp.
      1. Read the RX igess timestamp fom the 0x114 - 0x116 egistes i sequetial ode, statig with the 0x14 egiste. The PTP moito logic efeshes the 0x114 - 0x116 egistes cotet to ext data whe ead fom 0x116 egiste.
    10. Display the TX packet cotet, RX packet cotet, TX PTP commads, TX egess timestamp, ad RX igess timestamp ifomatio.
    11. Display the compaiso ifomatio. Note that i 1-step commads, the TX/RX packets ad PTP commads field cotet is the same.
    12. Repeat steps b though step k util the system pocesses all packets.
      Note: The desig example simulatio pefoms step 14 fo oly fist six packets to educe log simulatio time.
  15. Pefom Avalo® memoy-mapped iteface test o PTP-elated egistes.
    • Selective PTP Asymmety Delay ad P2P MeaPathDelay egistes
    • Selective Maste TOD Avalo® memoy-mapped iteface egistes
  16. Pefom Avalo® memoy-mapped iteface test. Wite ad ead Etheet IP egistes.
    • 0x104: Scatch egiste
    • 0x108: Etheet IP soft eset egiste
    • 0x214: TX MAC souce addess egiste [31:0]
    • 0x218: TX MAC souce addess egiste [47:32]
    • 0x21C: RX MAC fame size egiste
  17. Pefom Avalo® memoy-mapped iteface 2 test. Wite ad ead tasceive egistes.
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