GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 10/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance 6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance 7. Simulate, Compile, and Validate SyncE - Single Instance 8. Simulate and Compile PTP1588 - Single Instance 9. Simulate, Compile, and Validate - Multiple Instance 10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues A. Appendix A: Functional Description B. Appendix B: Configuration Registers C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex™ 5 Ethernet Portfolio and Target Applications 1.5. Agilex™ 5 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex™ 5 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance 4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Implement Clock Connections to MAC Asynchronous Operation 4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.5.1. Connect the MII PCS Mode TX Interface x
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface x
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.6.1. Connect the FlexE and OTN Mode TX Interface x
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and OTN Mode RX Interface x
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example 5.5. Validate the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
5.5. Validate the Design Example x
5.5.1. Configure the Clocks in Hardware 5.5.2. Program the FPGA 5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example 6.5. Validate the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
6.5. Validate the Design Example x
6.5.1. Configure the Clocks in Hardware 6.5.2. Program the FPGA 6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example 7.5. Validate the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow for Single Instance with SyncE 7.3.2. Simulator Output
7.5. Validate the Design Example x
7.5.1. Configure the Clocks in Hardware 7.5.2. Program the FPGA 7.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example 8.5. Validate the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
8.5. Validate the Design Example x
8.5.1. Configure the Clocks in Hardware 8.5.2. Program the FPGA 8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example 9.5. Validate the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow for MAC Mode 9.3.2. Simulator Output
9.5. Validate the Design Example x
9.5.1. Configure the Clocks in Hardware 9.5.2. Program the FPGA 9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training x
10.1. Design Example Features 10.2. Design Example Components 10.3. Simulate the Design Example 10.4. Compile the Design Example 10.5. Validate the Design Example
10.3. Simulate the Design Example x
10.3.1. Simulation Testbench Flow 10.3.2. Simulation Output
10.5. Validate the Design Example x
10.5.1. Configure the Clocks in Hardware 10.5.2. Program the FPGA 10.5.3. Run the Hardware Test
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence 11.3. Use Signal Tap Analyzer for Troubleshooting
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
A. Appendix A: Functional Description x
A.1. Datapath Description A.2. GTS Ethernet Intel® FPGA Hard IP MAC A.3. PCS, OTN, and FlexE Modes A.4. Precision Time Protocol Interface A.5. Auto-Negotiation and Link Training
A.2. GTS Ethernet Intel® FPGA Hard IP MAC x
A.2.1. MAC TX Datapath A.2.2. MAC RX Datapath A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) A.2.4. Link Fault Signaling A.2.5. Order of Ethernet Transmission:
A.2.1. MAC TX Datapath x
A.2.1.1. Insert TX Preamble, Start, and SFD A.2.1.2. Insert Source Address A.2.1.3. Process Length/Type Field A.2.1.4. Pad the Client Frame A.2.1.5. Insert Frame Check Sequence (CRC-32) A.2.1.6. Generate and Insert Inter-Packet Gap
A.2.2. MAC RX Datapath x
A.2.2.1. Process RX Preamble A.2.2.2. Check RX Strict SFD A.2.2.3. Check RX FCS A.2.2.4. Handle RX Malformed Packet A.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames A.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors A.2.2.7. Inter-Packet Gap
A.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
A.2.3.1. Conditions Triggering XOFF Frame Transmission A.2.3.2. Conditions Triggering XON Frame Transmission A.2.3.3. Pause Control and Generation Interface A.2.3.4. Pause Control Frame Filtering
A.3. PCS, OTN, and FlexE Modes x
A.3.1. PCS Mode A.3.2. OTN Mode A.3.3. FlexE Mode
A.4. Precision Time Protocol Interface x
A.4.1. Features A.4.2. PTP User Flow A.4.3. Make PTP UI Adjustments A.4.4. Reference Time Interval A.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
A.4.2. PTP User Flow x
A.4.2.1. PTP TX User Flow A.4.2.2. PTP RX User Flow
A.4.3. Make PTP UI Adjustments x
A.4.3.1. Adjust TX UI A.4.3.2. Adjust RX UI
B. Appendix B: Configuration Registers x
B.1. Ethernet Avalon® Memory-Mapped Interface Address Space B.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

3.2. Configure GTS Ethernet Hard IP

Pefom the followig steps to cofigue the GTS Etheet Itel® FPGA Had IP :
  1. Select Tools > IP Catalog to ope the IP Catalog.
  2. Select GTS Etheet Itel® FPGA Had IP (Libay > Iteface Potocols > GTS Etheet > Itel® FPGA Had IP ).
  3. Click Add.
  4. Specify a top-level ame <you_ip> ad the folde fo you custom IP vaiatio. The Paamete Edito saves the IP vaiatio settigs i a file amed <you_ip>.ip.
  5. Click Ceate. The IP paamete edito appeas as show i the figue below. The GTS Etheet Itel® FPGA Had IP has a IP tab, Example Desig tab, ad Aalog Paametes tab.
    Figue 4.  GTS Etheet Itel® FPGA Had IP Paametes: IP Tab
  6. O the IP tab, specify the paametes fo you IP coe vaiatio. Refe to the table below fo ifomatio about specific IP coe paametes.
Table 12.   GTS Etheet Itel® FPGA Had IP Paametes
Paamete Rage Default Settig Paamete Desciptio
Auto-Negotiatio ad Lik Taiig Optios
Eable auto-egotiatio ad lik taiig
  • Eable
  • Disable
 Disable Whe selected, the IP icludes additioal soft logic to pefom Auto-Negotiatio ad Lik Taiig (AN/LT).
Simulatio Optios
Eable Fast Simulatio
  • Eable
  • Disable
 Eable Eables fast simulatio i the geeated example desig fo Etheet IP, ad also eables fast simulatio i AN/LT IP, if AN/LT is eabled.
Note: If fast simulatio is eabled, the GTS Etheet Itel® FPGA Had IP skips auto-egotiatio ad lik taiig fuctioality ad updates the AN/LT status egistes to eflect AN/LT completio. To execise complete AN/LT fuctioality duig simulatio, disable the fast simulatio optio.
IP Tab : Geeal Optios
Cliet iteface
  • MAC Avalo® ST
  • MII PCS Oly
  • PCS66 OTN
  • PCS66 FlexE
 MAC Avalo® ST
Selects data iteface exposed to a cliet. Selected iteface detemies the Etheet fuctioal blocks eabled i the desig.
  • MAC Avalo® steamig iteface fo 10GE Etheet.
  • PCS66 Iteface fo OTN ad FlexE
PMA Refeece fequecy
  • 156.250000
  • 322.265625
  • 312.500000
 156. 250000
Selects the efeece clock fequecy used by the tasceive.
  • 156.25 MHz is the ecommeded fequecy fo 10GE Etheet mode.
  • 312.5 MHz is also suppoted whe AN/LT is ot used.
  • The fequecy 322.265625 MHz is suppoted whe you select IEEE 802.3 BASE-R Fiecode o RS(528,514), while usig without AN/LT.
System PLL fequecy
  • 322.265625
  • 805.664062
  • Custom
 322.265625
Selects the System PLL fequecy. The coe clock (o_clk_pll) is equivalet to this ate divided by 2.
  • 322.265625 MHz fo 10GE Etheet Mode.
  • 805.664062 MHz fo 25GE Etheet mode.
Custom System PLL Fequecy 322.265625 - 1000
  • 536.2500000
  • 805.6640625
 If you choose the Custom optio i the System PLL Fequecy paamete, the IP coe clock (o_clk_pll) is equivalet to half of the specified ate.
  • 536.2500000: Agilex™ 5 E-Seies (Device Goup B).
  • 805.6640625: Agilex™ 5 E-Seies (Device Goup A) ad D-seies.
Eable Dedicated CDR Clock Output
  • Eable
  • Disable
 Disable Whe selected, eables the dedicated CDR clock output. Each bak has oly oe such dedicated output.
PTP Optios Tab
Eable IEEE 1588 PTP
  • Eable
  • Disable
 Disable Eable this optio to add IEEE 1588 PTP Timestamp offload fuctios to the Coe. The coe ca geeate oe-step o two-step TX ad RX timestamps.
Timestamp figepit width
  • 8
  • 32
 8 Specify the timestamp figepit width i bits o the TX path. The default value is 8 bits.
Base_Pot > Pot #0 IP Cofiguatio
Etheet Mode
  • 10G-1
  • 25G-1
 10G-1 This optio defies seial lie ate.
FEC Mode
  • Noe
  • IEEE 802.3 BASE-R Fiecode (CL74)
  • IEEE 802.2 RS(528,514) (CL 91)
 Noe
Selects the FEC mode fo each pot.
  • Fiecode FEC oly suppoted fo 10GE Etheet Mode.
  • RS(528,514) oly suppots 25GE Etheet mode.
Base_Pot(Pot #0) > Pot #0 IP Cofiguatio > Pot #0 MAC Optio > P0 BasicBase
Ready latecy 0 - 3 0

Selects the eady Latecy value o the TX cliet iteface.

Ready Latecy is a Avalo® steamig iteface popety that defies the umbe of clock cycles of delay fom whe the IP coe assets the o_tx_eady sigal to the clock cycle i which the IP coe ca accept data o the TX cliet iteface. Refe to the Avalo® Iteface Specificatios.

Eable asychoous adapte clocks
  • Eable
  • Disable
 Disable

Whe tued o, you may dive the i_clk_x ad i_clk_tx clock sigals diffeet fom o_clk_pll clock.

Available oly whe Cliet iteface is set to MAC Avalo® steamig iteface.

TX Maximum Fame size 65 - 65,535 1518 Maximum packet size (i bytes) the IP coe ca tasmit o the Etheet lik without epotig a ovesized packet i the TX statistics coutes.
RX Maximum Fame size 65 - 65,535 1518

Maximum packet size (i bytes) the IP coe ca eceive o the Etheet lik without epotig a ovesized packet i the RX statistics coutes.

RX Fames lage tha TX Maximum fame size ae teated as ovesized.

If you tu o Efoce Maximum Fame Size paamete, the IP coe tucates icomig Etheet packets that exceed this size.

Efoce maximum fame size
  • Eable
  • Disable
 Disable Specifies whethe the IP coe ca eceive a ovesized packet o tucates these packets. I a tucated packet, eo sigal idicates ovesize ad FCS eo.
Lik fault geeatio optio
  • OFF
  • Uidiectioal
  • Bidiectioal
 OFF

Specifies the IP coe espose to lik fault evets. Bidiectioal lik fault hadlig complies with the Etheet specificatio, specifically IEEE 802.3 Figue 81-11.

Uidiectioal lik fault hadlig implemets IEEE 802.3 Clause 66: i espose to local faults, the IP coe tasmits Remote Fault odeed sets i itepacket gaps but does ot espod to icomig Remote Fault odeed sets.

The OFF optio is povided fo backwad compatibility.

Bytes to emove fom RX fames
  • Noe
  • Remove CRC bytes.
  • Remove CRC ad PAD bytes
 Noe Selects whethe the RX MAC must emove CRC bytes, o etai all bytes i icomig RX fames befoe passig them to the RX MAC Cliet. If the PAD bytes ad CRC ae ot eeded dowsteam, this optio ca educe the eed fo dowsteam packet pocessig logic.
Fowad RX pause equests
  • Eable
  • Disable
 Disable

Selects whethe the RX MAC fowads icomig PAUSE ad PFC fames o the RX cliet iteface o dops them afte iteal pocessig.

Note: If flow cotol is tued off, the IP coe fowads all icomig PAUSE ad PFC fames diectly to the RX cliet iteface ad pefoms o iteal pocessig. I that case this paamete has o effect.
Use souce addess isetio
  • Eable
  • Disable
 Disable

Selects whethe the IP coe suppots ovewitig the souce addess i a outgoig Etheet packet with the value i the TXMAC_SADDR egistes.

If the paamete is tued o, the IP coe ovewites the packet souce addess fom the egiste if i_tx_skip_cc has the value of 0.

If the paamete is tued off, the IP coe does ot ovewite the souce addess. Souce addess isetio applies to PAUSE ad PFC packets povided o the TX MAC cliet iteface but does ot apply to PAUSE ad PFC packets the IP coe tasmits i espose to the assetio of i_tx_pause o i_tx_pfc[] o the TX MAC cliet iteface.

TX MAC Souce Addess Stig “001122334455”

TX MAC Souce Addess default value to use as Souce Addess fo TX PAUSE/PFC packets ad whe Use Souce Addess Isetio is eabled.

Value is a 48-bit umbe witte i Hexadecimal.
TX VLAN detectio
  • Eable
  • Disable

Eable

Specifies whethe the IP coe TX statistics block teats TX VLAN ad Stacked VLAN Etheet fames as egula cotol fames, o pefoms Legth/Type field decodig, icludes these fames i VLAN statistics, ad couts the payload bytes istead of the full Etheet fame i the TxFameOctetsOK coute.

If tued o, the IP coe idetifies these fames i TX statistics as VLAN o Stacked VLAN fames. If tued off, the IP coe teats these fames as egula cotol fames.

RX VLAN detectio
  • Eable
  • Disable

Eable

Specifies whethe the IP coe RX statistics block teats RX VLAN ad Stacked VLAN Etheet fames as egula cotol fames, o pefoms Legth/Type field decodig, icludes these fames i VLAN statistics, ad couts the payload bytes istead of the full Etheet fame i the RxFameOctetsOK coute.

If tued o, the IP coe idetifies these fames i RX statistics as VLAN o Stacked VLAN fames. If tued off, the IP coe teats these fames as egula cotol fames.

Stop TX taffic whe lik pate seds PAUSE
  • No
  • Yes
  • Disable flow cotol
 No

Whe set to Yes, both SFC ad PFC ae suppoted. Whe a pause fame is eceived, the TX MAC stops sedig taffic.

Whe set to No, both SFC ad PFC ae suppoted. Whe a pause fame is eceived, the TX MAC does ot stop sedig taffic. Whe set to Disable, flow cotol is disabled etiely.

Base_Pot(Pot #0) > Pot #0 IP Cofiguatio > Pot #0 MAC Optio > P0 Specialized
Eable stict peamble check
  • Eable
  • Disable
 Disable

If tued o, the IP coe ejects RX packets whose peamble is ot the stadad Etheet peamble (0x55_55_55_55_55_55).

This optio povides a additioal laye of potectio agaist spuious Stat fames that ca occu at statup o whe bit eos occu.
Eable stict SFD check
  • Eable
  • Disable
 Disable

If tued o, the IP coe ejects RX packets whose SFD byte is ot the stadad Etheet SFD (0xD5).
Aveage Itepacket Gap
  • 1
  • 8
  • 10
  • 12
 12 Specifies the aveage miimum ite-packet gap (IPG) the IP coe maitais o the TX Etheet lik. Specifies the aveage miimum Ite-Packet Gap (IPG) the IP coe maitais o the TX Etheet lik. The default value of 12 complies with the Etheet stadad. The emaiig values suppot iceased thoughput. The value of 1 specifies that the IP coe tasmits Etheet packets as soo as the data is available, with the miimum possible gap. The IPG depeds o the space you leave betwee fame data as you wite it to the coe. The IP coe o loge complies with the Etheet stadad, but the applicatio has cotol ove the aveage gap ad maximizig the thoughput.
Eable peamble passthough
  • Eable
  • Disable
 Disable

If tued o, the IP coe is i RX ad TX peamble pass-though mode.

I RX peamble pass-though mode, the IP coe passes the peamble ad SFD to the cliet istead of stippig them out of the Etheet packet.

I TX peamble pass-though mode, the cliet specifies the peamble to be set i the Etheet fame.
Base_Pot(Pot #0) > Pot #0 IP Cofiguatio > Cofiguatios, Debug ad Extesio Optios
Eable debug edpoit fo tasceive toolkit
  • Eable
  • Disable
 Disable Eables the Tasceive toolkit.

Whe eabled, a embedded Native Phy Debug Edpoit coects iteally to the AVMM slave iteface fo the use of tasceive toolkit.
Eable debug edpoit fo Etheet toolkit
  • Eable
  • Disable
 Disable

Eables the Etheet toolkit

Whe eabled, a embedded Etheet Debug Edpoit coects iteally to the AVMM slave fo the use of Etheet toolkit.
Level Two Title