Visible to Intel only — GUID: qoq1698271644365
Ixiasoft
Visible to Intel only — GUID: qoq1698271644365
Ixiasoft
4. IP Architecture and Functional Description
This chapter describes the architecture details of the IP and details the various blocks and modes available in the IP that you can use. The following figure displays the IP block diagram, showing important blocks and their interfaces.
The IP gives you complete control over the PCIe* HIP. You can implement any functionality of interest with finer control over the PCIe* Transaction Layer Packet (TLP), credit handling and various modes provided by HIP.
On the transmit side, the IP forwards TLPs received from application to the Link. Your application user logic is responsible for constructing TLPs as per PCIe* rules, and for implementing credit management logic using the credit interfaces provided. The tag allocation and management are also done by the application user logic.
On the receive side, the IP sends TLPs received from Link to user side with some additional information like BAR number and function number. Apart from forwarding received TLPs, additional sideband interfaces are provided for error reporting, reading, and writing registers in Hard IP and reset handshake.
This mode also provides basic telemetry and debug functionality blocks.
The following table shows the various profiles available when using the IP. The profiles when selected will populate the below default settings in the Parameter Editor and can be used as a starting point by the user.
If you want settings that do not match any of the profiles, you can choose the Basic profile and configure the settings you want via the "expand" tabs. For example, you can choose 4 PFs in an Endpoint after choosing the Basic profile.
Profile | Default Parameter Editor Selections |
---|---|
Basic |
|
Basic + | All features from Basic Profile plus:
|
Virtual |
|
Virtual+ | All features from Virtual profile plus:
|
Section Content
Clocks and Resets
PCIe Hard IP (HIP)
HIP Interface (IF) Adaptor
Application Error Reporting
Debug Toolkit and Hard IP (HIP) Reconfiguration Interface
Configuration Space Extension
Control Shadow
Configuration Intercept Interface
Power Management
Legacy Interrupt
Credit Handling
Completion Timeout
Transaction Ordering
Page Request Service (PRS) Events
TX Non-Posted Metering Requirement on Application
MSI Pending
D-State Status
Configuration Retry Status Enable
AXI-Streaming Interface
Precision Time Measurement (PTM) [F/R-Tiles Only]