AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4. IP Architecture and Functional Description

This chapter describes the architecture details of the IP and details the various blocks and modes available in the IP that you can use. The following figure displays the IP block diagram, showing important blocks and their interfaces.

Figure 28.  AXI Streaming Intel® FPGA IP for PCI Express* Block Diagram

The IP gives you complete control over the PCIe* HIP. You can implement any functionality of interest with finer control over the PCIe* Transaction Layer Packet (TLP), credit handling and various modes provided by HIP.

On the transmit side, the IP forwards TLPs received from application to the Link. Your application user logic is responsible for constructing TLPs as per PCIe* rules, and for implementing credit management logic using the credit interfaces provided. The tag allocation and management are also done by the application user logic.

On the receive side, the IP sends TLPs received from Link to user side with some additional information like BAR number and function number. Apart from forwarding received TLPs, additional sideband interfaces are provided for error reporting, reading, and writing registers in Hard IP and reset handshake.

This mode also provides basic telemetry and debug functionality blocks.

The following table shows the various profiles available when using the IP. The profiles when selected will populate the below default settings in the Parameter Editor and can be used as a starting point by the user.

If you want settings that do not match any of the profiles, you can choose the Basic profile and configure the settings you want via the "expand" tabs. For example, you can choose 4 PFs in an Endpoint after choosing the Basic profile.

Table 27.  Functional Mode Profiles
Profile Default Parameter Editor Selections
Basic
  • One PF in an endpoint
  • One 64-bit BAR of 64 kB
  • AER enabled
  • Max payload size of 512 bytes
  • Maximum read request size (MRRS)=max supported by tile
  • Tags=max supported by tile
Basic +

All features from Basic Profile plus:

  • VirtIO PCIe* Capability present
  • FLR Enabled
  • MSI-X with 256 vectors
Virtual
  • Two Physical Functions (PF) in an Endpoint
  • PF0 has no Virtual Functions (Supervisory Role)
  • 128 Virtual Functions per PF
  • AER Enabled
  • FLR Enabled
  • All functions have one 64-bit BAR of 64Kbyte
  • MSI-X enabled with 4 vectors per function
  • ATS, TPH, PASID capabilities Enabled
  • Maximum Payload size is 512 Bytes
  • MRRS=Max Supported by Tile
  • Tags = Max Supported by Tile
Virtual+

All features from Virtual profile plus:

  • VirtIO PCI Capability Present
  • Four PFs in an endpoint