Visible to Intel only — GUID: idf1700109069356
Ixiasoft
Visible to Intel only — GUID: idf1700109069356
Ixiasoft
7.3.1.15. CFG RETRY CTRL
The application layer can use this register to update the per PF Configuration Retry Status Enable controls (CRS En Controls) driven to the Hard IP Controller. All VFs will share the same control as their parent PF. When the corresponding PF's CRS En Control is asserted, HardIP Controller will respond to configuration TLPs with a CRS (Configuration Retry Status) if it has not already responded to a Configuration TLP with non-CRS status since the last reset. You can use this to hold off on enumeration.
Default Value: 0x0000_0000
Register Name | Bit | Attribute User Side | Description |
---|---|---|---|
CFG RETRY CTRL | 0 | RW | Update CRS En Control Writing '1' to this bit causes the IP to update the corresponding CRS En Controls indicated by "Slot Number", "PF Index" and "PF Number". The IP clears this bit when the update is complete. Write to this bit is ignored if bit is already set |
5-1 | RW | Slot Number Indicates Slot Number of the CRS En Controls to be updated |
|
7-6 | RsvdZ | Reserved | |
9-8 | RW | PF Index Indicates which 8 Physical Functions of the CRS En Controls to be updated. 00 - PF7:PF0 01 - PF15:PF8 10 - PF23:PF16 11 - PF31:PF24
Note: Current Quartus release limits to max 8 PFs only.
|
|
15-10 | RsvdZ | Reserved | |
23-16 | RW | PF Number Indicates up-to 8 Physical Functions (one-hot) of the CRS En. Controls to be updated |
|
31-24 | RsvdZ | Reserved |