AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.6. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant

Table 17.  Simulating the AXI Streaming Intel® FPGA IP for PCI Express*
AXI Streaming Intel® FPGA IP for PCI Express* in Description
Standalone mode

You must create your own simulation environment to simulate and verify the functionality of the IP and design, based on the application requirement. You can also use third-party Bus Functional Models (BFMs), and Verification IPs (VIPs) to verify the IP in simulation.

The IP simulation files can be found in the /ip/sim/<simulator> folder in the Quartus® Prime project directory.

Design example

The simulation testbench (Intel BFM) for the IP is generated as part of the design example generation. Refer to the steps below for simulating the design example using the Intel BFM.

Intel Open FPGA Stack (OFS) reference design

Simulation environment for the IP and example workloads are provided as part of the reference design.

Note: For examples on simulating the IP with the Intel OFS reference design, contact your Intel Sales Representative for access to the Intel OFS design repository.