AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.13. VIRTIO PCI* Configuration Access Interface

The VIRTIO PCI* Configuration Access Interface is provided to allow application to implement the VIRTIO PCI* Configuration Access Data register functionality. The VIRTIO specification allows software to use the VIRTIO PCI* Configuration Access capability register as an alternative method to access VIRTIO device region. When this interface is enabled, the PCIe* IP provides a passage for the HIP's VIRTIO PCI* Configuration Access Interface to application logic. When this interface is disabled, the PCIe* IP internally drops writes from HIP's VIRTIO PCI* Configuration Access Interface and returns 0's for reads (per the requested byte length).

Note:
  1. Only the first 3 bits of QHIP's virtio_pcicfg_length_o[31:0] will be used since length is restricted by VIRTIO specification to be 1, 2 or 4 only.
  2. The QHIP's virtio_pcicfg_appvfnum_i and virtio_pcicfg_apppfnum_i are not used by QHIP. The PCIe* SS can tie-off these to 0's.
  3. The QHIP's virtio_pcicfg_rdbe_i[3:0] needs to be internally driven by PCIe* SS based on the pending read length on the st_virtio_pcicfgreq interface.
  4. When the QHIP is not instantiated, the VirtIO capability structure will be included in the SS.