AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.5.1. Configuration Intercept Request Interface (st_ciireq)

Table 57.  Configuration Intercept Request Interface
Signal Name Direction Clock Domain Description
ss_app_st_ciireq_tvalid Output axi_lite_clk When asserted, indicates a valid CFG request cycle is waiting to be intercepted. Deasserted when app_ss_st_ciireq_tready is asserted.
app_ss_st_cciireq_tready Input axi_lite_clk Application asserts this signal for one clock to acknowledge ss_app_st_ciireq_tvalid is seen by responder.
ss_app_st_ciireq_tdata[0] Output axi_lite_clk hdr_poisoned: The poisoned bit in the received TLP header on the CII.
ss_app_st_ciireq_tdata[4:1] Output axi_lite_clk hdr_first_be: The first dword byte enable field in the received TLP header on the CII.
ss_app_st_ciireq_tdata[9:5] Output axi_lite_clk slot_num: The slot number in the received TLP header on the CII.
ss_app_st_ciireq_tdata[12:10] Output axi_lite_clk func_num: The PF number in the received TLP header on the CII.
ss_app_st_ciireq_tdata[23:13] Output axi_lite_clk vf_num: The child VF number of parent PF in the received TLP header on the CII.
ss_app_st_ciireq_tdata[24] Output axi_lite_clk vf_active: Indicates VF number is valid in the received TLP header on the CII.
ss_app_st_ciireq_tdata[25] Output axi_lite_clk wr: Indicates a configuration write request detected in the received TLP header on the CII. Also, indicates that st_app_st_ciireq_tdata[67:36] is valid.
ss_app_st_ciireq_tdata[35:26] Output axi_lite_clk addr: The double word register address in the received TLP header on the CII.
ss_app_st_ciireq_tdata[71:36] Output axi_lite_clk dout: Received TLP payload data from the link partner to your application client. The data is in little endian format. The first received payload byte is in [43:36].

The following figure shows timing diagram for configuration write request indication to the application when intercept feature is not enabled.

The first command is a configuration write to PF1 byte-1 and byte-0 at address=0x200. The tvalid is high for 1 clock cycle as the application is ready to accept the packet.

The second command is a full dword configuration write to VF=26 of PF5 at address=0x3F0. As the application is not ready to accept the packet, sub-system holds the information till tready is seen

Figure 53. Configuration Write Request Indication