AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.8. Configuration Intercept Interface

The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior. The application logic should detect the CFG request at the assertion of ss_app_st_ciireq_tvalid on the ss_app_st_ciireq* interface.

The application logic can use the CII to:

  • Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first. This can be achieved by withholding the assertion of app_ss_st_ciireq_tready.
  • Overwrite the data payload of a CfgWr request. The application logic can also overwrite the data payload of a CfgRd completion TLP. This can be achieved using the app_ss_st_ciiresp* interface.
Note:
  1. This interface is provided so that the IP is backward compatible with legacy application logic that relies on CII for their functionality. Newly defined application logic should avoid using the CII interface and move to the CEB interface.
  2. The CEB interface and the CII interface are mutually exclusive. Hence, both cannot be enabled at the same time.
Note: Refer to Interfaces and Signals for details on the interface signals.