AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.3.13. TX CPL DATA

The register indicates completion data transmitted by the IP.

Default Value: 0x0000_0000

Table 103.  TX CPL DATA Registers
Register Name Bit Attribute User Side Description
TX CPL DATA 31-0 RW1C

Bytes Transferred

32'h00000000 - No bytes

32'h00000001 - 1 KB

32'h00000002 - 2 KB

…….

32'hFFFFFFFF - 4 TB