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1. Introduction
2. Features
3. Getting Started with the AXI Streaming Intel® FPGA IP for PCI Express*
4. IP Architecture and Functional Description
5. AXI Streaming Intel® FPGA IP for PCI Express* Parameters
6. Interfaces and Signals
7. Register Descriptions
8. Document Revision History for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Specifications
B. Simulating the Design Example
1.1. Goal of the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
1.2. Intended Audience for the AXI Streaming Intel® FPGA IP for PCI Express* User Guide
1.3. What is PCI Express* ?
1.4. What are the Intel® FPGA IPs for PCI Express* ?
1.5. What is the AXI Streaming Intel® FPGA IP for PCI Express* ?
1.6. Example Use Models
1.7. Design Flow Requirements
3.1. Download and Install Quartus Software
3.2. Obtain and Install Intel FPGA IPs and Licenses
3.3. Configure and Generate the AXI Streaming Intel® FPGA IP for PCI Express*
3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples
3.5. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces
3.6. Simulate the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.7. Compile the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.8. Software Drivers for AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.9. Build the Application for the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.10. Verification with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
3.11. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant
4.1. Clocks and Resets
4.2. PCIe Hard IP (HIP)
4.3. HIP Interface (IF) Adaptor
4.4. Application Error Reporting
4.5. Debug Toolkit and Hard IP (HIP) Reconfiguration Interface
4.6. Configuration Space Extension
4.7. Control Shadow
4.8. Configuration Intercept Interface
4.9. Power Management
4.10. Legacy Interrupt
4.11. Credit Handling
4.12. Completion Timeout
4.13. Transaction Ordering
4.14. Page Request Service (PRS) Events
4.15. TX Non-Posted Metering Requirement on Application
4.16. MSI Pending
4.17. D-State Status
4.18. Configuration Retry Status Enable
4.19. AXI-Streaming Interface
4.20. Precision Time Measurement (PTM) [F/R-Tiles Only]
6.1. Overview
6.2. Clocks and Resets
6.3. Application Packet Interface
6.4. Configuration Extension Bus Interface
6.5. Configuration Intercept Interface
6.6. Function Level Reset Interface
6.7. Control Shadow Interface (st_ctrlshadow)
6.8. Completion Timeout Interface (st_cplto)
6.9. Miscellaneous Signals
6.10. Control and Status Register Responder Interface (lite_csr)
6.11. Error Interface (st_err)
6.12. VF Error Flag Interface (vf_err/sent_vfnonfatalmsg)
6.13. VIRTIO PCI* Configuration Access Interface
6.14. Serial Data Signals
7.3.1.1. AXI Streaming Intel® FPGA IP for PCI Express* Version
7.3.1.2. AXI Streaming Intel® FPGA IP for PCI Express* Features
7.3.1.3. AXI Streaming Intel® FPGA IP for PCI Express* Interface Attributes
7.3.1.4. HOT PLUG GEN CTRL
7.3.1.5. POWER MANAGEMENT CTRL
7.3.1.6. LEGACY INTERRUPT CTRL
7.3.1.7. CFG REG IA CTRL
7.3.1.8. CFG REG IA FN NUM
7.3.1.9. CFG REG IA WRDATA
7.3.1.10. CFG REG IA RDDATA
7.3.1.11. PRS CTRL
7.3.1.12. MSI PENDING CTRL
7.3.1.13. MSI PENDING
7.3.1.14. D-STATE STS
7.3.1.15. CFG RETRY CTRL
7.3.3.1. PERFMON CTRL
7.3.3.2. TX MRD TLP
7.3.3.3. TX MWR TLP
7.3.3.4. TX MSG TLP
7.3.3.5. TX CFGWR TLP
7.3.3.6. TX CFGRD TLP
7.3.3.7. RX MRD TLP
7.3.3.8. RX MWR TLP
7.3.3.9. RX MSG TLP
7.3.3.10. RX CFGWR TLP
7.3.3.11. RX CFGRD TLP
7.3.3.12. TX MEM DATA
7.3.3.13. TX CPL DATA
7.3.3.14. RX MEM DATA
7.3.3.15. RX CPL DATA
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3.4.3. Functional Description for the Performance Design Example
The Performance design example performs memory transfers from the AXI Streaming Intel FPGA IP for PCI Express to the host system memory. You can configure the Endpoint Traffic Generator design example to send:
- Memory Write-only TLPs
- Memory Read-only TLPs
- Both Memory Write and Memory Read TLPs
There is a traffic counter implemented in the FPGA Application logic to measure the amount of traffic that is being generated. To make a traffic measurement, the software application running at the host side issues a memory read TLP, acquires the counter value, and prints the traffic generated on the system terminal. The software application performs a memory write to the control register within the Application logic to start and stop the traffic.
Port Mode | Link Width | Topology | Link Speed | HIP Data Width (Bits) | Application Data Width (Bits) | Compact/HIP Native Mode | Design Example Support |
---|---|---|---|---|---|---|---|
Endpoint | x16 | 1x16 | Gen4 | 512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH |
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH | |||
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x8 | 2x8 1x8 |
Gen4 | 256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | |
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | |||
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x4 | 4x4 | Gen4 | 128 (1 x 128) | 256 (1 x 256) | Compact | CT | |
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
Gen3 | 128 (1 x 128) | 256 (1 x 256) | Compact | CT | |||
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
2x4 1x4 |
Gen4 | 128 (1 x 128) | 256 (1 x 256) | Compact | CTH | ||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Gen3 | 128 (1 x 128) | 256 (1 x 256) | Compact | CTH | |||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Root Port | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
TL Bypass | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
Note: For the P-Tile AXI Streaming Performance design example, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Port Mode | Link Width | Topology | Link Speed | HIP Data Width (Bits) | Application Data Width (Bits) | Compact/HIP Native Mode | Design Example Support |
---|---|---|---|---|---|---|---|
Endpoint | x16 | 1x16 | Gen4 | 512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH |
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH | |||
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x8 | 2x8 1x8 |
Gen4 | 256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | |
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | |||
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x4 | 4x4 | Gen4 | 128 (1 x 128) | 256 (1 x 256) | Compact | CT | |
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
Gen3 | 128 (1 x 128) | 256 (1 x 256) | Compact | CT | |||
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
2x4 1x4 |
Gen4 | 128 (1 x 128) | 256 (1 x 256) | Compact | CTH | ||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Gen3 | 128 (1 x 128) | 256 (1 x 256) | Compact | CTH | |||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Root Port | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
TL Bypass | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
PIPE Direct (PIPE-D) | 1x16 | Gen4 | 512 (2 x 256) | 512 (2 x 256) | Compact | S | |
PIPE Direct (PIPE-D) | 2x8 | Gen4 | 512 (2 x 256) | 512 (2 x 256) | Compact | S | |
PIPE Direct (PIPE-D) | 1x8 | Gen4 | 256 (1 x 256) | 256 (1 x 256) | Compact | S |
Note: For the F-Tile AXI Streaming Performance design example, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Port Mode | Link Width | Topology | Link Speed | HIP Data Width (Bits) | Application Data Width (Bits) | Compact/HIP Native Mode | Design Example Support |
---|---|---|---|---|---|---|---|
Endpoint | x16 | 1x16 | Gen5 | 1024 (4 x 256) | 1024 (4 x 256) | HIP Native | SCTH |
1024 (4 x 256) | 1024 (4 x 256) | Compact | SCTH | ||||
1024 (4 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
1024 (4 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
1024 (4 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
1024 (4 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
1024 (4 x 256) | 256 ( 1 x 256) | Compact | SCTH | ||||
Gen4 | 1024 (4 x 256) | 1024 (4 x 256) | HIP Native | SCTH | |||
512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | HIP Native | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 1024 (4 x 256) | 1024 (4 x 256) | HIP Native | SCTH | |||
512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | HIP Native | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x8 | 2x8 1x8 |
Gen5 | 512 (2 x 256) | 1024 (4 x 256) | Compact | SCTH | |
512 (2 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | HIP Native | SCTH | ||||
512 (2 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
512 (2 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
512 (2 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen4 | 512 (2 x 256) | 512 (2 x 256) | HIP Native | SCTH | |||
256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | HIP Native | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
Gen3 | 512 (2 x 256) | 512 (2 x 256) | HIP Native | SCTH | |||
256 (1 x 256) | 1024 (4 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (2 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 1024 (1 x 1024) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (2 x 256) | Compact | SCTH | ||||
256 (1 x 256) | 512 (1 x 512) | Compact | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | HIP Native | SCTH | ||||
256 (1 x 256) | 256 (1 x 256) | Compact | SCTH | ||||
x4 | 4x4 | Gen5 | 256 (2 x 128) | 1024 (4 x 256) | Compact | CT | |
256 (2 x 128) | 1024 (2 x 512) | Compact | CT | ||||
256 (2 x 128) | 1024 (1 x 1024) | Compact | CT | ||||
256 (2 x 128) | 512 (2 x 256) | Compact | CT | ||||
256 (2 x 128) | 512 (1 x 512) | Compact | CT | ||||
256 (2 x 128) | 256 (2 x 128) | HIP Native | CTH | ||||
256 (2 x 128) | 256 (2 x 128) | Compact | CT | ||||
256 (2 x 128) | 256 (1 x 256) | Compact | CT | ||||
Gen4 | 256 (2 x 128) | 256 (2 x 128) | HIP Native | CTH | |||
128 (1 x 128) | 256 (1 x 256) | Compact | CT | ||||
128 (1 x 128) | 128 (1 x 128) | HIP Native | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
Gen3 | 256 (2 x 128) | 256 (2 x 128) | HIP Native | CTH | |||
128 (1 x 128) | 256 (1 x 256) | Compact | CT | ||||
128 (1 x 128) | 128 (1 x 128) | HIP Native | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | Compact | CT | ||||
2x4 1x4 |
Gen4 | 256 (2 x 128) | 256 (2 x 128) | HIP Native (1x4) | CTH | ||
128 (1 x 128) | 256 (1 x 256) | Compact | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | HIP Native | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Gen3 | 256 (2 x 128) | 256 (2 x 128) | HIP Native (1x4) | CTH | |||
128 (1 x 128) | 256 (1 x 256) | Compact | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | HIP Native | CTH | ||||
128 (1 x 128) | 128 (1 x 128) | Compact | CTH | ||||
Root Port | N/A | N/A | N/A | N/A | N/A | N/A | |
TL Bypass | N/A | N/A | N/A | N/A | N/A | N/A | |
PIPE Direct (PIPE-D) | 1x16 | Gen5 | 1024 (4 x 256) | 1024 (4 x 256) | HIP Native / Compact | S | |
PIPE Direct (PIPE-D) | 2x8 | Gen5 | 512 (2 x 256) | 512 (2 x 256) | HIP Native / Compact | S |
Note: For the R-Tile AXI Streaming Performance design example in Endpoint mode, only VCS, and VCSMX are supported for simulation.
Note: The R-Tile AXI Streaming Performance design example in PIPE Direct mode is only supported by VCS.
Figure 15. Performance AXI Streaming 1x16, 1x8, 1x4 Design Example Block Diagram
Figure 16. Performance AXI Streaming 2x8, 2x4 Design Example Block Diagram
Figure 17. Performance AXI Streaming 4x4 Design Example Block Diagram
Figure 18. Gen5 Performance Design Example Block Diagram