AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.4.3. Functional Description for the Performance Design Example

The Performance design example performs memory transfers from the AXI Streaming Intel FPGA IP for PCI Express to the host system memory. You can configure the Endpoint Traffic Generator design example to send:
  • Memory Write-only TLPs
  • Memory Read-only TLPs
  • Both Memory Write and Memory Read TLPs

There is a traffic counter implemented in the FPGA Application logic to measure the amount of traffic that is being generated. To make a traffic measurement, the software application running at the host side issues a memory read TLP, acquires the counter value, and prints the traffic generated on the system terminal. The software application performs a memory write to the control register within the Application logic to start and stop the traffic.

Table 14.  Performance AXI Streaming Design Example Supported Configurations (P-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Topology Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 1x16 Gen4 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 2x8

1x8

Gen4 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 4x4 Gen4 128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) Compact CT
Gen3 128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) Compact CT
2x4

1x4

Gen4 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port N/A N/A N/A N/A N/A N/A N/A
TL Bypass N/A N/A N/A N/A N/A N/A N/A
Note: For the P-Tile AXI Streaming Performance design example, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Table 15.  Performance AXI Streaming Design Example Supported Configurations (F-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Topology Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 1x16 Gen4 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 2x8

1x8

Gen4 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 4x4 Gen4 128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) Compact CT
Gen3 128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) Compact CT
2x4

1x4

Gen4 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port N/A N/A N/A N/A N/A N/A N/A
TL Bypass N/A N/A N/A N/A N/A N/A N/A
PIPE Direct (PIPE-D)   1x16 Gen4 512 (2 x 256) 512 (2 x 256) Compact S
PIPE Direct (PIPE-D)   2x8 Gen4 512 (2 x 256) 512 (2 x 256) Compact S
PIPE Direct (PIPE-D)   1x8 Gen4 256 (1 x 256) 256 (1 x 256) Compact S
Note: For the F-Tile AXI Streaming Performance design example, only VCS, VCSMX, Questasim, and Modelsim are supported for simulation.
Table 16.  Performance AXI Streaming Design Example Supported Configurations (R-Tile)Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Port Mode Link Width Topology Link Speed HIP Data Width (Bits) Application Data Width (Bits) Compact/HIP Native Mode Design Example Support
Endpoint x16 1x16 Gen5 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
1024 (4 x 256) 1024 (4 x 256) Compact SCTH
1024 (4 x 256) 1024 (2 x 512) Compact SCTH
1024 (4 x 256) 1024 (1 x 1024) Compact SCTH
1024 (4 x 256) 512 (2 x 256) Compact SCTH
1024 (4 x 256) 512 (1 x 512) Compact SCTH
1024 (4 x 256) 256 ( 1 x 256) Compact SCTH
Gen4 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen3 1024 (4 x 256) 1024 (4 x 256) HIP Native SCTH
512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
x8 2x8

1x8

Gen5 512 (2 x 256) 1024 (4 x 256) Compact SCTH
512 (2 x 256) 1024 (2 x 512) Compact SCTH
512 (2 x 256) 1024 (1 x 1024) Compact SCTH
512 (2 x 256) 512 (2 x 256) HIP Native SCTH
512 (2 x 256) 512 (2 x 256) Compact SCTH
512 (2 x 256) 512 (1 x 512) Compact SCTH
512 (2 x 256) 256 (1 x 256) Compact SCTH
Gen4 512 (2 x 256) 512 (2 x 256) HIP Native SCTH
256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) HIP Native SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
Gen3 512 (2 x 256) 512 (2 x 256) HIP Native SCTH
256 (1 x 256) 1024 (4 x 256) Compact SCTH
256 (1 x 256) 1024 (2 x 512) Compact SCTH
256 (1 x 256) 1024 (1 x 1024) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (2 x 256) Compact SCTH
256 (1 x 256) 512 (1 x 512) Compact SCTH
256 (1 x 256) 256 (1 x 256) HIP Native SCTH
256 (1 x 256) 256 (1 x 256) Compact SCTH
x4 4x4 Gen5 256 (2 x 128) 1024 (4 x 256) Compact CT
256 (2 x 128) 1024 (2 x 512) Compact CT
256 (2 x 128) 1024 (1 x 1024) Compact CT
256 (2 x 128) 512 (2 x 256) Compact CT
256 (2 x 128) 512 (1 x 512) Compact CT
256 (2 x 128) 256 (2 x 128) HIP Native CTH
256 (2 x 128) 256 (2 x 128) Compact CT
256 (2 x 128) 256 (1 x 256) Compact CT
Gen4 256 (2 x 128) 256 (2 x 128) HIP Native CTH
128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CT
Gen3 256 (2 x 128) 256 (2 x 128) HIP Native CTH
128 (1 x 128) 256 (1 x 256) Compact CT
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CT
2x4

1x4

Gen4 256 (2 x 128) 256 (2 x 128) HIP Native (1x4) CTH
128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Gen3 256 (2 x 128) 256 (2 x 128) HIP Native (1x4) CTH
128 (1 x 128) 256 (1 x 256) Compact CTH
128 (1 x 128) 128 (1 x 128) HIP Native CTH
128 (1 x 128) 128 (1 x 128) Compact CTH
Root Port N/A   N/A N/A N/A N/A N/A
TL Bypass N/A   N/A N/A N/A N/A N/A
PIPE Direct (PIPE-D)   1x16 Gen5 1024 (4 x 256) 1024 (4 x 256) HIP Native / Compact S
PIPE Direct (PIPE-D)   2x8 Gen5 512 (2 x 256) 512 (2 x 256) HIP Native / Compact S
Note: For the R-Tile AXI Streaming Performance design example in Endpoint mode, only VCS, and VCSMX are supported for simulation.
Note: The R-Tile AXI Streaming Performance design example in PIPE Direct mode is only supported by VCS.
Figure 15. Performance AXI Streaming 1x16, 1x8, 1x4 Design Example Block Diagram
Figure 16. Performance AXI Streaming 2x8, 2x4 Design Example Block Diagram
Figure 17. Performance AXI Streaming 4x4 Design Example Block Diagram
Figure 18. Gen5 Performance Design Example Block Diagram