Visible to Intel only — GUID: zud1720019491993
Ixiasoft
Visible to Intel only — GUID: zud1720019491993
Ixiasoft
6.11. Error Interface (st_err)
This interface is applicable for Endpoint and Root Port modes.
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
app_ss_st_err_tvalid | Input | axi_lite_clk | When asserted, the app_ss_st_err_tvalid indicates that the application is reporting an error. |
app_ss_st_err_tdata[31:0] | Input | axi_lite_clk | The app_ss_st_err_tdata carries the function number info, 128-bit header and 32-bit TLP prefix over multiple cycles (32 bits of information are sent in each clock cycle).
Cycle 1: Carries the following information:
Cycle 2: TLP header[31:0] Cycle 3: TLP header[63:32] Cycle 4: TLP header[95:64] Cycle 5: TLP header[127:96] Cycle 6: TLP prefix Depending on Bit[17] and Bit[18]. tdata is valid for 1, 5, or 6 cycles. |
app_ss_st_err_tuser_error_type[13:0] | Input | axi_lite_clk |
Indicates the error type:
|
app_ss_st_err_tlast | Input | axi_lite_clk | Indicates the last cycle of app_ss_st_err_tdata transfer. The app_ss_st_err_tlast is asserted on the 1st, 5th, or 6th cycle of tdata depending on the "TLP header will follow / TLP Prefix will follow" bits. |
ss_app_st_err_tready | Output | axi_lite_clk | When deasserted, this signal indicates back-to-back user inputs cannot be processed. |