AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.3.8.1. Application Transmit Flow Control Credit Interface (st_txcrdt)

On the Transmit side, the link partner's receive buffer space information is provided to the application through the Transmit Flow Control Credit Interface for P/F/R-Tiles. Apart from the AXI streaming ready valid handshake, the application logic must check for the availability of credits on the TX flow control credit interface before transmitting the TLP.

Table 51.  Application Transmit Flow Control Credit Interface
Signal Name Direction Clock Domain Description
ss_app_st_txcrdt_tvalid Output axi_st_clk tvalid indicates that the credit information on tdata is valid.
ss_app_st_txcrdt_tdata[18:0] Output axi_st_clk Carries the credit limit information and type of credit.

[15:0] - Credit Limit Value

[18:16] - Credit Type
  • 3'b000 - Posted Header Credit
  • 3'b001 - Non-Posted Header Credit
  • 3'b010 - Completion Header Credit
  • 3'b011 - Reserved
  • 3'b100 - Posted Data Credit
  • 3'b101 - Non-Posted Data Credit
  • 3'b110 - Completion Data Credit
  • 3'b111 - Reserved
Note: Although infinite credits may be advertised, the IP may still backpressure on the st_tx interface.

The figure below shows the credit limit update on the Transmit Flow Control Credit Interface.

In the example below, updated credit limit is output from cycle 9 to cycle 14. When the HOST returns the credit after receiving the packet, the credit limit is incremented by the number of credits returned. At cycle 16, one Posted Header credit is returned. At cycle 19, four Posted Data credits are returned.