AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.3.10. RX CFGWR TLP

The register indicates the number of configuration write TLPs received by the IP.

Default Value: 0x0000_0000

Table 100.  RX CFGWR TLP Registers
Register Name Bit Attribute User Side Description
RX CFGWR TLP 31-0 RW1C Number of Configuration Write TLPs