Visible to Intel only — GUID: lnk1697836857155
Ixiasoft
Visible to Intel only — GUID: lnk1697836857155
Ixiasoft
1. Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 3.0.0 |
The AXI Streaming Intel® FPGA IP for PCI Express* allows you to implement PCI Express* (PCIe) in your design using Intel’s technology leading PCIe* hardened protocol stack with an AXI4 user interface. The IP includes the hardened transaction, data link and physical layers, as well as optional blocks and interface adapters to interface with Direct Memory Access (DMA) and Scalable Switch Intel FPGA IPs for applications requiring high-bandwidth data transfer between the host or virtual machine and the I/O devices. This document introduces the various Intel FPGA PCI Express IP offerings and details the AXI Streaming Intel® FPGA IP for PCI Express* , including features and functional descriptions of the various blocks within the IP. This document also describes the design flow requirements and guidelines, IP parameters, interfaces, and signals available to you when you use this IP.
Section Content
Goal of the AXI Streaming Intel FPGA IP for PCI Express User Guide
Intended Audience for the AXI Streaming Intel FPGA IP for PCI Express User Guide
What is PCI Express ?
What are the Intel FPGA IPs for PCI Express ?
What is the AXI Streaming Intel FPGA IP for PCI Express ?
Example Use Models
Design Flow Requirements