AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.1.6. LEGACY INTERRUPT CTRL

Default Value : 0x0000_0000

Table 77.  Legacy Interrupt Control Register
Register Name Bit Attribute User Side Description
LEGACY INTERRUPT CTRL 0 RW

Assert Message

The application sets this bit when it wants to send assert message.

The IP passes on this information to HIP block and clears this bit indicating requested operation complete.

1 RW

Deassert Message

The application sets this bit when it want to send deassert message.

The IP passes on this information to HIP block and clears this bit indicating requested operation complete.

15-4 RsvdZ Reserved
20-16 RW

PF Number

Indicates PF Number of Function generating Assert or Deassert message.

Note: Current Quartus release limits to max 8 PFs only.
31-21 RsvdZ Reserved