AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.1. Clocks and Resets

The AXI Streaming Intel® FPGA IP for PCI Express* has the following clock domains to drive the various interfaces.

Table 28.  Clock domains in the AXI Streaming Intel® FPGA IP for PCI Express*
Clock Domain Description
core_clk

This clock is synchronous to the SerDes parallel clock

Gen4/Gen5: 1000 MHz

Gen3: 500 MHz

Gen2: 250 MHz

Gen1: 125 MHz

coreclkout_hip_toapp

The coreclkout_hip output of the HIP drives this clock. Application can use this clock to generate PCIe* IP clocks.

Gen4/Gen5: 500 MHz

Gen3: 250 MHz

Gen2/Gen1: Gen1/Gen2 is supported only via link down-training and not natively. Hence, the coreclkout_hip_toapp clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz.

axi_st_clk

This global clock signal is an input to the IP. This clock is used to clock the AXI-ST Datapath interfaces (TX, RX) to the application logic. All signals of the AXI-ST Datapath interface are sampled on the rising edge of axi_st_clk.

The frequency of this clock depends on the mode in which the IP is configured:
  • In Native HIP mode, this clock uses the Hard IP's coreclkout_hip.
  • In non-Native HIP mode, the clock frequency can be selectable based on the speed of the link as shown below:
    • Gen5/Gen4: 500/470/400/350/250 MHz (32-, 64-, 128-byte widths)
    • Gen3: 300/275/250 MHz (32-, 64-byte widths)
axi_lite_clk

This global clock signal is an input to the IP. This clock is used to clock the sideband interfaces, e.g., control and status register interface, completion timeout interface, etc. All signals are sampled on the rising edge of axi_lite_clk.

Frequency: 100-250 MHz (Default 250MHz)

The figure below shows clock domains in the IP. All the clocks must be always on for the correct functioning of a design.

Figure 29. Clock Domains in the AXI Streaming Intel® FPGA IP for PCI Express*

The AXI Streaming Intel® FPGA IP for PCI Express* has two types of resets:

  • Bus Resets - The bus resets are AXI specification defined reset signals, which are used to reset the logic in the IP interfacing with AXI fabric.
  • IP Resets - The IP reset signals perform cold/warm reset sequences.

You must implement a user reset sequencer in the application user logic and follow the assertion and deassertion sequence for graceful entry and exit for each of the resets (cold, warm etc). Refer to Clocks and Resets for the sequence to be followed for these reset signals.

The IP has the following reset domains to drive the various interfaces.

Table 29.  Reset Domains in the AXI Streaming Intel® FPGA IP for PCI Express*
Reset Domain Type Description
Cold reset IP reset A Reset following the application of power. This will reset the following:
  • Bus resets (AXI-ST/AXI-Lite)
  • Hard IP
  • Sticky registers of configuration space
  • When cold reset is triggered, warm reset and bus resets must be asserted

Refer to PCI Express* Base Specification Revision 5.0 for more details on warm reset.

Warm reset IP reset A Fundamental Reset without cycling main power. This will reset the following:
  • Bus resets (AXI-ST/AXI-Lite)
  • Hard IP
  • The warm reset can be triggered multiple times by user without going through cold reset sequence.
  • When warm reset is triggered, Bus resets must be asserted

Refer to PCI Express* Base Specification Revision 5.0 for more details on warm reset.

AXI-ST reset Bus reset This will reset the AXI-ST main data path interface (e.g., AXI-ST TX/RX)
AXI-Lite reset Bus reset This will reset the AXI-Lite sideband interfaces (e.g., Completion timeout, control and status register)

The following figure indicates the reset domains in the IP.

Figure 30. Reset Domains

The list below specifies reset sequencing handshake requirement. The user must implement the reset sequencer in application user logic and follow the assertion and deassertion sequence for graceful entry and exit from reset.

Reset assertion:

  • Assertion happens concurrently for all.

Reset deassertion:

  • Cold reset
    • Req/Rdy handshake is used for graceful reset entry and exit.
  • Warm reset
    • Req/Rdy handshake is used for graceful reset entry and exit.
  • AXI4-Lite reset