AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

4.13. Transaction Ordering

The IP does not have separate receiving queues to handle PCIe* transaction ordering or prevent deadlocks. The application logic needs to ensure the transactions adhere to PCIe* ordering rules that prevent deadlocks, namely:

  • Allow posted writes to pass blocked read transactions.
  • Allow posted writes to pass blocked configuration write transactions.
  • Allow completion to pass blocked read transactions.
  • Allow completion to pass blocked configuration write transactions.