AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

7.3.2.5. HIA RX BP CYCLES

The register indicates back pressure cycles observed because HIP interface adaptor receive interface was not ready to accept transactions.

Default Value: 0x0000_0000

Table 90.  HIA RX BP Registers
Register Name Bit Attribute User Side Description
HIA RX BP CYCLES 30-0 RW1C Back Pressure Cycle Count
31 RW1C Indicates Overflow, cycle count reached 31'h7FFFFFFFF