AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.11. Debugging with the AXI Streaming Intel® FPGA IP for PCI Express* IP Variant

Typically, PCI Express* link-up involves the following steps:

  1. Link training
  2. BIOS enumeration and data transfer

This section describes the flow to debug link issues during the hardware bring-up. Intel recommends a systematic approach to diagnosing issues as illustrated in the following figure.

You can use the following Quartus tools to identify the issues:
  • Intel Quartus Signal Tap II Analyzer
  • In-System Sources and Probes (ISSP) tools

Additionally, you can use the IP Debug Toolkit for debugging the PCIe* links when using the AXI Streaming Intel® FPGA IP for PCI Express* . The Debug Toolkit includes the following features:

  • Protocol and link status information
  • Basic and advanced debugging capabilities including register read access and Eye viewing capability
  • System Console based interface to access status registers of the AXI Streaming Intel® FPGA IP for PCI Express* IP using scripts
Figure 25. PCI Express Debug Flow Chart