AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

6.4.2. Configuration Extension Bus Response Interface (st_cebresp)

The application returns read data for requests received from "st_cebreq" interface using "st_cebresp" interface. The IP is always ready to accept responses from the application. The application will provide response data with valid qualifier.

This interface is mutually exclusive with the Configuration Intercept Response Interface.

Table 56.  Configuration Extension Bus Response Interface
Signal Name Direction Clock Domain Description
app_ss_st_cebresp_tvalid Input axi_lite_clk Application assert this signal for one clock to indicate that valid data is driven on app_ss_st_cebresp_tdata bus.
app_ss_st_cebresp_tdata[31:0] Input axi_lite_clk Response data from application for read request issued using "st_cebreq interface".

The following figure shows timing diagram for back-to-back write and read command; the first command sends write for all four bytes of register located at address=4. The second command sends write for byte3 and byte2 of same register. The third command sends read for same register. Upon receiving the read command on st_cebreq interface, the application returns data on st_cebresp interface. You must note that the data returned is 5621. The upper two bytes were modified by the second write.

Figure 52. Timing Diagram for Configuration Extension Bus Response Interface